speeding up simulations - PCIE example

[mistercoffee]

Hi,

I can see I'm not the first person to post something like this, but I haven't seen anything elsewhere for my specific case that would help.

I am in Vivado Sim with 2014.2 and I am simulating a modified version of the PCIE endpoint example design, using the supplied testbench. It takes approx 45 mins for me to get to the 100us point. I note that it takes 63us before the transaction reset is deasserted.

How can I speed this up? I have tried the unifast enable, and I need to monitor signals so I cannot turn off the debug level.

I seems to be getting slower as the simulation progresses. IS this due to the size of the wdb getting larger and taking longer to write to?

It would be really nice to get this simulation time down in some way. Even some way to fool the core into finishing it's link training would help guess.

Thanks

[brasilino · Accepted solution]

Hi,

Are you using Virtex-7 or any 7 series FPGAs?

Try to enable PIPE simulation on the core by selecting 'Enable Pipe Simulation' before you generate (I mean 'open) the Example Design. Doing so the EP should be simulated using PIPE.

Also, I suggest you to read about PIPE in Integrated Block docs.

regards

[mistercoffee]

 Hi,

Thanks for the reply. I hasn't seen that section yet (this is a big PG!).

However, I am using the VHDL model, that's just what we use to program in. It seems it is only available in the verilog model?

FTR, I using a Kintex 7 and the IP version is 3.0

Thanks

James

[mistercoffee]

I am tempted to try a mixed language sim. I can use all the verilog example files apart from the user app modules and then replace them with my own VHDL files. This might work I guess?

[mistercoffee]

FYI, this appears to work. For simulation I should be able to make some decent progress with this method. It now runs in less than 10 minutes.

Possible bug alert...

It is worth point out that simply disabling the verilog user app files in the example project was not enough to tell the simulator to not use them. I had my vhdl equivalents imported and enabled, and I could see from the file tree that they were the files being instantiated by the parent module. Despite this the simulation ran with the disabled verilog modules. However, once I actually removed the verilog modules from the project, it then ran as expected, using the vhdl modules...