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Registered: ‎11-16-2014

synthesis problem for floating point arithmetic

Hi there,

 

I am recently writing a project using floating point arithmetic. I have already read a lot of documents for floating point arithmetic. I have downloaded the package files from http://www.vhdl.org/fphdl/ wrote by David Bishop, which are really helpful. I have successfully finished the IP block for an adjustable digital audio amplifier using fixed point arithmetic by using the ieee_proposed.fixed_pkg.all. The target gain and the speed of the audio change can be modified.

However when I am using floating point arithmetic I have encountered big problems. Many signals are thrown away after synthesis, and I just have no idea how to change my code. It works quite well when I using fixed point arithmetic. Hope someone to help.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 12/16/2014 08:58:32 AM
-- Design Name: 
-- Module Name: volume_adjust - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

library ieee_proposed;
use ieee_proposed.fixed_float_types.all; -- ieee in the release
use ieee_proposed.float_pkg.all; 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity volume_adjust is
    Port (  
        clk_96kHz : in STD_LOGIC; 
        rstn : in STD_LOGIC;
        bypass : in STD_LOGIC;
        Audio_In : in STD_LOGIC_VECTOR(31 downto 0);
        Audio_Out : out STD_LOGIC_VECTOR(31 downto 0);
        Target_Gain : in STD_LOGIC_VECTOR(31 downto 0);
        Fading_coeff : in STD_LOGIC_VECTOR(31 downto 0)
    );
end volume_adjust;

architecture Behavioral of volume_adjust is

constant zero : float32 := to_float(0,8,23);
constant one : float32 := to_float(1,8,23);

signal current_gain_float: float32 := zero;
--attribute keep : string;
--attribute keep of current_gain_float : signal is "true";

signal gain_temp: float32 := zero;
signal target_gain_float:float32 := one;
--attribute keep of target_gain_float : signal is "true";

signal audio_in_float :float32;
--attribute keep of audio_in_float : signal is "true";

signal audio_out_float : float32 ;

signal fading_coeff_float: float32 := zero;
--attribute keep of fading_coeff_float : signal is "true";
--signal audio_out_slv: std_logic_vector(31 downto 0);

begin
    --type conversion
    --synchronised input
--    process(rstn,clk_96kHz)
--    begin
--        if(rstn = '0')then
--            audio_in_float <= zero;
--            target_gain_float <= zero;
--            fading_coeff_float <= zero;
--        elsif(rising_edge(clk_96kHz)) then
--            audio_in_float <= to_float(audio_in,8,23);
--            target_gain_float<=to_float(target_gain,8,23);
--            fading_coeff_float<=to_float(fading_coeff,8,23);
--        end if;
--    end process;
    
-- unsynchronised input audio_in_float <= to_float(audio_in,8,23); target_gain_float<=to_float(target_gain,8,23); fading_coeff_float<=to_float(fading_coeff,8,23);
--update gain process (rstn, clk_96kHz) begin if(rstn = '0') then current_gain_float<= zero; elsif (clk_96kHz'event and clk_96kHz = '1')then current_gain_float<= Gain_temp; end if; end process;
-- calculate gain process(bypass, rstn, Target_Gain_float, current_gain_float, fading_coeff_float) begin if(rstn = '0') then gain_temp <= zero; elsif (bypass = '1') then gain_temp <= one; elsif (lt(current_gain_float,target_gain_float)) then if lt(add(current_gain_float, fading_coeff_float), target_gain_float) then Gain_temp <= add( current_gain_float,fading_coeff_float); else Gain_temp <= (Target_Gain_float); end if; elsif gt(current_gain_float,target_gain_float) then if gt(subtract(current_gain_float,fading_coeff_float), target_gain_float) then Gain_temp <= subtract(current_gain_float, fading_coeff_float); else Gain_temp <= (Target_Gain_float); end if; else Gain_temp <= (Target_Gain_float); end if; end process;
--calculate output Audio_out_float <= Audio_in_float * current_gain_float; audio_out <= to_slv(audio_out_float); end Behavioral;

 warnings_floating_point.png

 

 

 

There are the following warnings after synthesis:

 

The main warnings are;

[Synth 8-63] RTL assertion: "float_pkg:BREAK_NUMBER: Meta state detected in fp_break_number process" ["U:/Praktikum/volume_adjust/volume_adjust.srcs/sources_1/imports/xilinx_11/float_pkg_c.vhdl":1515]

[Synth 8-3332] Sequential element (\current_gain_float_reg[7] ) is unused and will be removed from module volume_adjust.

 

However, actually in schematic the signal fading_coeff are not connected with other signals. Part of the schematic is shown as followed:

The small black spot in the left top of the picture is fading_coeff. It is not connected.

 

As you may have seen above, I have already tried the keep attribute, but it won't help. I am just wondering if anyone can help me to solve this problem. I have stucked at it for quite a few days. I have tried fast everything I come up with, but just haven't got a solution. Perhaps need I extra algorithms to implement floating point arithmetic?

 

However, both the simulation for behavioral and post synthesis seems to be right.

behav:

behav.png

post_synth_func:

post_synq_func.png

 

 

There is no error showed, the simulation seems to be right, but my system don't work correctly. There is a lot of noise at output, which apparently I don't want.

 

 

The following is the vhdl file for fixed arithmetic, which works well.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/04/2014 08:19:41 AM
-- Design Name:
-- Module Name: lvs_fixed_user_logic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: volume adjustment using fixed point arithmentics
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
library IEEE_proposed;
use ieee_proposed.fixed_float_types.all; -- ieee in the release
use ieee_proposed.fixed_pkg.all;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity lvs_fixed_user_logic is
       Port (
           clk_96kHz : in STD_LOGIC;
           rstn : in STD_LOGIC;
           bypass : in STD_LOGIC;
          Audio_In : in STD_LOGIC_VECTOR(31 downto 0);
           Audio_Out : out STD_LOGIC_VECTOR(31 downto 0);
           Target_Gain : in STD_LOGIC_VECTOR(31 downto 0);
           Fading_coeff : in STD_LOGIC_VECTOR(31 downto 0)
           );
end lvs_fixed_user_logic;
 
architecture Behavioral of lvs_fixed_user_logic is
 
signal current_gain: sfixed(8 downto -23);
signal gain_temp: sfixed(8 downto -23) ;
signal target_gain_fixed: sfixed(8 downto -23);
signal audio_in_fixed :sfixed(8 downto -23);
signal audio_out_fixed : sfixed(8 downto -23) ;
signal fading_coeff_fixed: sfixed(8 downto -23);

begin
   --type conversion
   audio_in_fixed <= to_sfixed(audio_in, audio_in_fixed);
   target_gain_fixed<=to_sfixed(target_gain, target_gain_fixed);
   fading_coeff_fixed<=to_sfixed(fading_coeff, fading_coeff_fixed);

   --updata gain
   process (clk_96kHz)
   begin
       if (clk_96kHz'event and clk_96kHz = '1')then
           current_gain <= Gain_temp;
       end if;
   end process;

--calculate next gain process(Target_Gain_fixed, current_gain, fading_coeff_fixed, bypass, rstn) begin if(rstn= '0')then gain_temp <= to_sfixed(0, gain_temp); elsif (bypass = '1')then gain_temp <= to_sfixed(1, gain_temp); elsif (current_gain < target_gain_fixed and current_gain + fading_coeff_fixed <= target_gain_fixed) then Gain_temp <= resize((current_gain + fading_coeff_fixed),gain_temp); elsif (current_gain > target_gain_fixed and current_gain - fading_coeff_fixed >= target_gain_fixed) then Gain_temp <= resize((current_gain - fading_coeff_fixed),gain_temp); else Gain_temp <= (Target_Gain_fixed); end if; end process; --calculate output Audio_out_fixed <= resize((Audio_in_fixed * current_gain),audio_out_fixed); audio_out <= to_slv(audio_out_fixed); end Behavioral;

 

 

 

I have attached my projects below If you need further information to help me, please let me know. Thanks a lot for your help.

I am using vivado 2014.3. And I am not considering using the Vivado HLS at the first time. I am just confusing why floating point arithmetic will not be correctly synthesized.

 

 

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