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Visitor yaelg
Visitor
973 Views
Registered: ‎02-04-2018

system verilog support

Hi,

I have not found any documentation about existing UVM support in Vivado logic sim, nor have I found any regarding SVA support. Is it safe to assume they are not currently supported?

 

Thanks

Yael

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Moderator
Moderator
964 Views
Registered: ‎09-15-2016

Re: system verilog support

Hi @yaelg

 

UVM is not yet supported with Vivado simulator. To know about all the supported SV constructs in Vivado simulator, refer Appendix B below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug900-vivado-logic-simulation.pdf

 

Regards

Rohit

Regards
Rohit
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Newbie hjackson
Newbie
850 Views
Registered: ‎03-22-2018

Re: system verilog support

Hi Rohit,

 

Thanks for pointing at the simulator document. It actually implies in the document that you can use it for UVM, also looking through the support table seems to suggest it covers most things.

 

I was also wondering if SVA is supported. This is not mentioned in the table (that I can see).

 

Thanks again,

 

Hugh

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