08-18-2020 08:14 AM
Vivado 2020 raises the warnings like the one below
WARNING: [XSIM 43-4100] "/wrk/2020.1/continuous/2020_05_27_2902540/data/verilog/src/unisims/IBUF.v" Line 29. Module IBUF has a timescale but at least one module in design doesn't have timescale.
The only design files without timescale instruction are the packages storing parameters (nothing time-related), user types definitions, and functions. Does the timescale omitting in these files affect the project in any way?
08-18-2020 08:41 AM
You can use -timescale option to add timescale to the files where it is missing OR use option -relax at elaboration stage to transform error into warning.
08-18-2020 10:28 AM
Thanks for the reply! But does adding timescale instruction (in any way) make any sense for simulation or some other purpose? In other words, is it Vivado being too cautious at this point, or maybe I do not understand something clearly?