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Visitor
Visitor
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Registered: ‎01-23-2019

unexpected results in simulation

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Hi all,

I have a mind-bending question regarding weird results in simulation. I am trying to enable a clock output by setting or clearing an enable register based on the state of 5 input signals: watchdog_en_n, check_pulse_i, thisAP_out, thatAP_out & cross_check_pulse_i.  The code used to change the enable signal is:

 

 

-- clock enable signal
process(clk)
begin
    if(rising_edge(clk)) then

-- use truth table to determine the state of the clock generater enable signal case std_logic_vector'(watchdog_en_n & check_pulse_i & thisAP_out & thatAP_out & cross_check_pulse_i) is when "00000" | "00001" | "00011" => thisAP_in_en <= '1'; when others => thisAP_in_en <= '0'; end case;
end if; end process;


I wrote a test bench to test all possible input combinations. The result is shown below:

clock enable.png

From the VHDL code, I would expect thisAP_in_en to only be '1' in three case, and every other case it would be '0'. But for some reason, thisAP_in_en is '1' when I expect it to be, but ALSO is '1' when watchdog_en_n = '0' and check_pulse = '1' and thisAP_out = '0'.

 

Can anyone offer any insight as to why this might be the case??! The process above is the only process that writes to the signal although it is read a couple of other places.

 

Thanks!

 

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Highlighted
Visitor
Visitor
439 Views
Registered: ‎01-23-2019

OK, so my bad.

 

after posting this I noticed that I was controlling cross_check_pulse and check_pulse, NOT cross_check_pulse_i and check_pulse_i

 

Derp.

 

Thanks!

View solution in original post

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Visitor
Visitor
453 Views
Registered: ‎01-23-2019

Sorry, I should also have mentioned that I am using Vivado 2018.1

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Highlighted
Visitor
Visitor
440 Views
Registered: ‎01-23-2019

OK, so my bad.

 

after posting this I noticed that I was controlling cross_check_pulse and check_pulse, NOT cross_check_pulse_i and check_pulse_i

 

Derp.

 

Thanks!

View solution in original post

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