cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
9,959 Views
Registered: ‎12-21-2007

using text test vector files with ISE10.1

I have use the waveform based test bench with ISE and used text test vectors with Modelsim (Iread them using $readmemb or $readmemh, ..) , Now I have 900 point test vector I want to use it to simulate a design in ISE. I wrote the test bench (fixture) in verilog but the simulator tells me that $readmem is not supported. How can use a text file as input to a simulation?  Thanks
0 Kudos
8 Replies
Highlighted
Xilinx Employee
Xilinx Employee
9,943 Views
Registered: ‎08-15-2007

Re: using text test vector files with ISE10.1

ISim currently works best if using the file_open function to read a file.  For example:

 

file_open(input_file, "source.bmp", read_mode);
read(input_file, char1);

 

The input file needs some header information prior to reading it.  To obtain this header information,  first write out a binary file from ISIM.  Then copy the header information generated by ISIM from the new binary file into the binary file you'd like to read in.

 

Efforts are being conducted to improve read/write file operations.  We apologize for the inconvenience.

Eddie
0 Kudos
Highlighted
Visitor
Visitor
9,927 Views
Registered: ‎12-21-2007

Re: using text test vector files with ISE10.1

What is ISim? Please start from ISE10.1 and tell me the steps to read a test vector. I am attaching the test bench verilog code (which worked with modelsim)
0 Kudos
Highlighted
Historian
Historian
9,920 Views
Registered: ‎02-25-2008

Re: using text test vector files with ISE10.1


cap_1952 wrote:
What is ISim? Please start from ISE10.1 and tell me the steps to read a test vector. I am attaching the test bench verilog code (which worked with modelsim)

You said, "Now I have 900 point test vector I want to use it to simulate a design in ISE." So edv assumed that you wanted to use the ISE Simulator, ISIM.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Visitor
Visitor
9,917 Views
Registered: ‎12-21-2007

Re: using text test vector files with inspect

Yes I want to use ISE simulator, as I said I wrote a verilog test bench and I got a message that $readmemd is not supported, my question was how to read a text test vector using ISE simulator. I cannot enter 900 values in waveform tb and visually inspect the output. The instructions from edv, while I appreciate the input, were totally unintelligible.

 

0 Kudos
Highlighted
Historian
Historian
9,905 Views
Registered: ‎02-25-2008

Re: using text test vector files with inspect


cap_1952 wrote:
Yes I want to use ISE simulator, as I said I wrote a verilog test bench and I got a message that $readmemd is not supported, my question was how to read a text test vector using ISE simulator. I cannot enter 900 values in waveform tb and visually inspect the output. The instructions from edv, while I appreciate the input, were totally unintelligible.

 


His reply made perfect sense.

 

Your question did not.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Visitor
Visitor
9,903 Views
Registered: ‎12-21-2007

Re: using text test vector files with inspect

bassman59

 

If you don't have anything helpful to say, please stay out of this thread.

0 Kudos
Highlighted
Historian
Historian
9,838 Views
Registered: ‎02-25-2008

Re: using text test vector files with inspect


cap_1952 wrote:

bassman59

 

If you don't have anything helpful to say, please stay out of this thread.


It is not for you to tell other users whether they should participate in any thread.

 

Good luck, you need it,

-a

----------------------------Yes, I do this for a living.
Highlighted
Xilinx Employee
Xilinx Employee
9,768 Views
Registered: ‎08-15-2007

Re: using text test vector files with inspect

We worked through a WebCase to resolve the issue.  There were a few problems with cap_1952's approach:

 

1) ISim only supports $readmemh and $readmemb for Verilog file input tasks.  cap_1952 was using a different readmem function.

2) He experienced issues writing out to a file via $fwrite verilog task.  The problem was due to an if conditional never being true and thus the function was never called.  Following modifications to his test bench, the simulation can now write to an output file.

 

 

Eddie
0 Kudos