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Visitor aimatee
Visitor
663 Views
Registered: ‎02-24-2018

vcs-mx co-sim Xilinx timing netlist

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Hi,

 

I am using vcs-mx co-sim Xilinx timing netlist with a systemc testbench?

 

I always get errors like this.

 

Error: [Unisim IBUFCTRL-103] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance sYsTeMcToP.top_inst.clk_IBUF_inst.IBUFCTRL_INST.

 

Lookint at the unisims library file, it has the following.

 

`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif

 

So, it does not detect  XIL_TIMING defined.

However, the netlist.v I used in the simulation does have `define XIL_TIMING on the top. I also have +define+XIL_TIMING in the vlogan command.

Why does the library still complain about it?

 

Any advice would be appreciated! Thanks!

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1 Solution

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Moderator
Moderator
764 Views
Registered: ‎04-24-2013

Re: vcs-mx co-sim Xilinx timing netlist

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Hi @aimatee,

 

What version of Vivado and VCS are you using?

 

Have you compiled the simulation libraries using either the tools or the compile_simlib command.

You can then use export_simulation command with the –lib_map_path switch to point to to them and check within the scripts generated.

 

Best Regards
Aidan

 

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Moderator
Moderator
765 Views
Registered: ‎04-24-2013

Re: vcs-mx co-sim Xilinx timing netlist

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Hi @aimatee,

 

What version of Vivado and VCS are you using?

 

Have you compiled the simulation libraries using either the tools or the compile_simlib command.

You can then use export_simulation command with the –lib_map_path switch to point to to them and check within the scripts generated.

 

Best Regards
Aidan

 

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
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Visitor aimatee
Visitor
583 Views
Registered: ‎02-24-2018

Re: vcs-mx co-sim Xilinx timing netlist

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Thanks for the reply.

 

I went to another machine that has both vcs and vivado and checked the scripts vivado generated as you suggested.

 

I used the exact elaboration scripts and it worked.

 

+pulse_r/0 +pulse_int_r/0 +pulse_e/0 +pulse_int_e/0 -liblist simprims_ver -liblist secureip

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