03-26-2015 10:24 PM
i had written verilog code in order to find remainder when we divide two numbers but i face one problem.....my algorithm is
i have 'q' dividend and 'm' divisor, 'rem' is remainder.....so if(q>m)
q=q-m otherwise rem=q
i write its verilog code but in that if statemnet runs for once....in next clock cycle it take value of p=q which i dont want i want my value in p comes as p=p-m;
module div(q,clk,rem,p,count ); parameter m=13'd840; input [12:0] q; input clk; output reg [12:0] rem; output reg [3:0] count; output reg [12:0] p; initial begin count=4'b0; //+ rem=9'b0; //p=13'b0; end always@(posedge clk) begin p=q; if (p>m) begin p=p-m; count=count+1; rem=p; end else rem=9'b0; end endmodule
04-06-2015 08:21 AM
04-06-2015 10:59 AM
Couple of things. One, if you intend to synthesize your design, then the modulus operator '%' has restrictions - the divisor can only be a power of two. So dprasad's solution would NOT work.
If you're just playing around with simulation, then yes, that solution is fine.
In any case, some more comments on your original code. Ask yourself - "how does the operation begin. I.e. when do you initialize count to zero, and set p=q? How long (in clock cycles) does it take to calculate my remainder? When can I change my input 'q' and have it calculate a new remainder?