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Visitor phil_0031
Visitor
569 Views
Registered: ‎09-19-2018

verilog vcdplusfile for VCD trace

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Hello 

 

My verilog testbench includes $vcdplusfile verilog keyword to specify the name of the vcd file read from command line argument (define testplusarg optionnal option for the simulator in project mode IDE configuration).

The elaboration phase fails with message error Undefined system task '$vcdplusfile'.

 

Command from the tcl console

Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 802e51d0e3344121bca5287de4f8cc57 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot core_testbench_behav xil_defaultlib.core_testbench xil_defaultlib.glbl -log elaborate.log

core_testbench.v code

...

initial begin
    // Where to store VPD trace file.
    if($value$plusargs("vcd=%s", vcdplusfilename))
      $vcdplusfile(vcdplusfilename);

...

 

I do not understand seems that vcdplusfile keyword is not recognized ?

Do I miss something in elaboration option ?

 

Thanks for help

 

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Moderator
Moderator
533 Views
Registered: ‎04-24-2013

Re: verilog vcdplusfile for VCD trace

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Hi @phil_0031,

 

To the best of my knowledge this is not supported in Vivado simulator.

 

It is included in the list of Verilog language support exceptions included in User Guide 900 Chapter G.

 

Best Regards
Aidan

 

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Moderator
Moderator
534 Views
Registered: ‎04-24-2013

Re: verilog vcdplusfile for VCD trace

Jump to solution

Hi @phil_0031,

 

To the best of my knowledge this is not supported in Vivado simulator.

 

It is included in the list of Verilog language support exceptions included in User Guide 900 Chapter G.

 

Best Regards
Aidan

 

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