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Anonymous
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vhpcomp vhdl version

Hello,

 

I'm trying to use a construct from VHDL-2008 in my code, the all keyword in a sensitivity list (see below).

 

do_stuff : process(all)

begin

    ...

end process;

 

I'm using vhpcomp/fuse to simulate the design. When I use vhpcomp on this code it gives me the error:

ERROR:HDLCompiler:1580 - "source/implementation/base/correlator.vhd" Line 292: Construct illegal in this mode of VHDL

 

Is there a way to specify the version of VHDL you want to use with vhpcomp? I tried creating a ISE project with VHDL-200X as its source code analysis standard and then using the vhpcomp -ise option, but that didn't work.

 

Colin

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Historian
Historian
5,352 Views
Registered: ‎02-25-2008

Re: vhpcomp vhdl version


@Anonymous wrote:

Hello,

 

I'm trying to use a construct from VHDL-2008 in my code, the all keyword in a sensitivity list (see below).

 

do_stuff : process(all)

begin

    ...

end process;

 

I'm using vhpcomp/fuse to simulate the design. When I use vhpcomp on this code it gives me the error:

ERROR:HDLCompiler:1580 - "source/implementation/base/correlator.vhd" Line 292: Construct illegal in this mode of VHDL

 

Is there a way to specify the version of VHDL you want to use with vhpcomp? I tried creating a ISE project with VHDL-200X as its source code analysis standard and then using the vhpcomp -ise option, but that didn't work.

 

Colin


I don't think that any of the Xilinx tools support VHDL-2008.

----------------------------Yes, I do this for a living.
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Teacher
Teacher
5,343 Views
Registered: ‎09-09-2010

Re: vhpcomp vhdl version

As stated in a separate thread, the synthsizer's Style Guide has the definitive information on how to write your code. Just be grateful that you don't have to write in VHDL-87 anymore.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Visitor
Visitor
5,302 Views
Registered: ‎11-07-2010

Re: vhpcomp vhdl version

> Just be grateful that you don't have to write in VHDL-87 anymore.

 

I don't know if there is any VHDL tool still used today that support only VHDL-87, but VHDL-87 is 24 years old and its first update was 18 years ago (VHDL-93). So we can normally expect that we don't have to write in VHDL-87 in any VHDL tool that is more or less modern.

 

Jonas

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Visitor
Visitor
5,287 Views
Registered: ‎11-07-2010

Re: vhpcomp vhdl version

Strangely "all" is recognized as a VHDL keyword both by the ISE text editor and the compiler so that it is impossible to name a signal "all" (even if the property "VHDL Source Analysis Standard" is set to VHDL-93 instead of VHDL-200X), but if we try to use it in a process sensivity list, we get the "Construct illegal in this mode of VHDL" error.

I am wondering if the problem is simply that the property "VHDL Source Analysis Standard" isn't passed to the xst command.

 

Jonas

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Teacher
Teacher
5,284 Views
Registered: ‎09-09-2010

Re: vhpcomp vhdl version

Of course 'all' is recognised as a keyword! It has been a keyword since VHDL-87. For example:
use ieee.std_logic_1164.all;

Just go and read UG627 and/or UG687 and/or UG660.

 


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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