03-05-2009 05:01 AM
I'm using xilinx 10.1.03 and ModelsimXC 6.3c.
Say I've a design in which there are several child modules. While I wish to integeate all together, lot of nets will be internal nets. However I want to see there transitions in wave window. How do I do it? Espicially when we go for Post-Route simulation the signal names are no longer what we assign. They are now in terms of internal buffer or mux output signals. So how do I go about this problem?
It's fine when we do Behavioral simulation however I'm dealing with Post-Route simulation. Please help.
03-05-2009 06:06 PM - edited 03-05-2009 06:07 PM
The implementation tools, by default, will "flatten" the design, meaning, there will no longer be an easily identifiable hierarchical boundary between the child modules in your design. A flattened netlist, as you point out, does not lend itself for thorough Post-PAR verification. Thus, you need to change some synthesis and implementation tool options in order to keep the design hierarchy.
To do so:
1) In Synthesis properties, select "Yes" for "Keep Hierarchy"
2) In Map properties, make sure the checkbox for "Allow Logic Optimization Across Hierarchy" is checked off.
3) In "Simulate Post-Place and Route" properties, under "Simulation Model", make sure the checkbox for "Retain Hierarchy" is checked.
Following this steps should result in a Post-PAR simulation model with retained hierarchy, which should help your debugging efforts at this stage.