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Registered: ‎01-20-2009

viewing internal signals

hi edv,

I'm using xilinx 10.1.03 and ModelsimXC 6.3c.

Say I've a design in which there are several child modules. While I wish to integeate all together, lot of nets will be internal nets. However I want to see there transitions in wave window. How do I do it? Espicially when we go for Post-Route simulation the signal names are no longer what we assign. They are now in terms of internal buffer or mux output signals. So how do I go about this problem?


It's fine when we do Behavioral simulation however I'm dealing with Post-Route simulation. Please help.



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Xilinx Employee
Xilinx Employee
Registered: ‎08-15-2007

Re: viewing internal signals



The implementation tools, by default, will "flatten" the design, meaning, there will no longer be an easily identifiable hierarchical boundary between the child modules in your design.   A flattened netlist, as you point out, does not lend itself for thorough Post-PAR verification.  Thus, you need to change some synthesis and implementation tool options in order to keep the design hierarchy.


To do so:


1) In Synthesis properties,  select "Yes" for "Keep Hierarchy"

2) In Map properties, make sure the checkbox for "Allow Logic Optimization Across Hierarchy" is checked off.

3) In "Simulate Post-Place and Route" properties, under "Simulation Model", make sure the checkbox for "Retain Hierarchy" is checked.


Following this steps should result in a Post-PAR simulation model with retained hierarchy, which should help your debugging efforts at this stage.  


Some notes:


  • Due to optimization by both synthesis and the implementation tools, it is possible that some internal signals will be renamed, or even removed.  As such, do not expect a complete 1:1 signal correspondence between behavioral and Post-PAR simulation results.
  • Due to added logic to maintain hierarchical boundaries, typically a hierarchical netlist has lower timing performance in comparison to a flattened netlist.  This is a drawback when implementing a design while keeping hierarchy.  If you find that the flattened netlist meets timing performance, while the hierarchical netlist doesn't, you should consider keeping hierarchy only on the modules of interest (instead of a global fashion).  This can be done by using the "keep_hierarchy" HDL attribute or UCF parameter.  Refer to the Constraints Guide for more information about this attribute.

Hope this helps.
Message Edited by edv on 03-05-2009 06:07 PM
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