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Visitor dannna
Visitor
10,064 Views
Registered: ‎03-04-2015

vivado simulation - block memory module failure

Hi,

 

I'm simulating a project with my own IPs. one of the IPs has a block memory generator (8.2).

The simulation stops after 35 ns and tck message:

 

Block Memory Generator module TOP030815.design_1_i.golgol_0.U0.blk_mem_gen_GOLAY_inst.inst.native_mem_module.blk_mem_gen_v8_2_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
Failure: ERROR:add_1 must be in range [-1,DEPTH-1]
Time: 35 ns Iteration: 2
$finish called at time : 35 ns : File "../../../project_1.srcs/sources_1/ipshared/ornim.medical/golgol_v1_0/a6138b30/hdl/golgol_v1_0.vhd" Line 93
xsim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:34 . Memory (MB): peak = 980.820 ; gain = 37.723
INFO: [USF-XSim-96] XSim completed. Design snapshot 'TOP030815_behav' loaded.

 

what is the problem? 

 

Thanks,

Danna

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5 Replies
Xilinx Employee
Xilinx Employee
10,054 Views
Registered: ‎07-16-2008

Re: vivado simulation - block memory module failure

Did you use the AXI4 interface for the block memory generator IP?

This kind of failure is typically seen when master and slave AXI are not initialized. e.g. when the slave TVALID and TDATA are in an 'U' or 'X' state.
 
You need to firstly examine the testbench (or the AXI bus drivers) and ensure they're all initialized.
For instance,
  -- Data slave channel signals
  signal s_axis_data_tvalid              : std_logic := '0';  -- payload is valid
  signal s_axis_data_tready              : std_logic := '1';  -- slave is ready
  signal s_axis_data_tdata               : std_logic_vector(15 downto 0) := (others => '0');  -- data payload
 
  -- Data master channel signals
  signal m_axis_data_tvalid              : std_logic := '0';  -- payload is valid
  signal m_axis_data_tdata               : std_logic_vector(23 downto 0) := (others => '0');  -- data payload
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
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Highlighted
Visitor dannna
Visitor
10,027 Views
Registered: ‎03-04-2015

Re: vivado simulation - block memory module failure

I'm using a native block memory and not an AXI interface,

 

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Moderator
Moderator
9,915 Views
Registered: ‎04-17-2011

Re: vivado simulation - block memory module failure

Also, check the clock stimulus in testbench. Take the following stimulus for example,
process begin
clk_153m <= not clk_153m;
wait for clk_cyc_153m / 2;
end process;

The clock edge is occurring before the register initializations have propagated to all connecting signals.

The solution is to rephrase the clock process such that the wait statement occurs before the toggle of the clock signal.
process begin
wait for clk_cyc_153m / 2;
clk_153m <= not clk_153m;
end process;
Regards,
Debraj
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Moderator
Moderator
9,799 Views
Registered: ‎04-17-2011

Re: vivado simulation - block memory module failure

@danna Is the issue closed based on the suggestions provided? If you have a solution you can post it and close this thread.
Regards,
Debraj
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Explorer
Explorer
3,356 Views
Registered: ‎05-23-2017

Re: vivado simulation - block memory module failure

@dannna,

Didi you find the solution for this problem. 

I am going through the same problem now.

 

Thanks.

Sean

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