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ysonera
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Registered: ‎02-25-2019

(vopt-7063) Failed to find 'inst' in hierarchical name

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I'm getting the following error from Questasim when starting the simulation. Questasim does not seem to find 'inst' in the testbench hierarchy. These are tasks from the Zynq MPSOC verification IP which I'm using per the example in DS941 page 10. Just confirm that I had the correct hierarchy path I created an example Zynq MPSOC project and confirmed that the generated testbench uses the same hierarchy (with different instance names) with 'inst' at the end. I also commented out the line which allowed me to start the simulation and inspect the hierarchy in Questasim. Questasim does not report any errors during compilation of the RTL or the SystemVerilog testbench. 

# vsim -voptargs="+acc" -t ps -L zynq_ultra_ps_e_vip_v1_0_6 -L unisim -L unisims_ver work.esa_xr_tb
# Start time: 13:53:20 on Mar 13,2021
# Loading C:/Users/ysonera/AppData/Local/Temp\ysonera@MBP03059_dpi_67200\win64_gcc-4.5.0\export_tramp.dll
# ** Note: (vsim-3812) Design is being optimized...
# ** Error (suppressible): ../src/tb/esa_xr_tb.sv(158): (vopt-7063) Failed to find 'inst' in hierarchical name 'esa_xr_tb.dut.u_xr_uzev_ps.xr_uzev_ps_i.inst.set_verbosity'.
# Region: esa_xr_tb
# ** Error (suppressible): ../src/tb/esa_xr_tb.sv(160): (vopt-7063) Failed to find 'inst' in hierarchical name 'esa_xr_tb.dut.u_xr_uzev_ps.xr_uzev_ps_i.inst.por_srstb_reset'.
# Region: esa_xr_tb
# ** Error (suppressible): ../src/tb/esa_xr_tb.sv(163): (vopt-7063) Failed to find 'inst' in hierarchical name 'esa_xr_tb.dut.u_xr_uzev_ps.xr_uzev_ps_i.inst.fpga_soft_reset'.
# Region: esa_xr_tb
# Optimization failed
# Error loading design

esa_xr_tb.sv(158-167): 

    `PS_INST.set_verbosity(32'd400); // Full verbosity
    $display ("%0t [ps]: Reseting verification IP", $time);
    `PS_INST.por_srstb_reset(1'b1);
    #(2*PS_CLK_PERIODD);
    `PS_INST.por_srstb_reset(1'b0);
    `PS_INST.fpga_soft_reset(32'h1);
    #(20*PS_CLK_PERIODD);  // This delay depends on your clock frequency. It should be at least 16 clock cycles.
    `PS_INST.por_srstb_reset(1'b1);
    `PS_INST.fpga_soft_reset(32'h0);
    #(100*PS_CLK_PERIODD); // Wait for internal adc_clk

where:

`define PS_INST esa_xr_tb.dut.u_xr_uzev_ps.xr_uzev_ps_i.inst

 

 

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graces
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Registered: ‎07-16-2008

Are yourunning simulation in Questasim alone with custom script?  I'd suggest that you run Export > Export Simulation in Vivado IDE to export simulation script for the design targetting Questasim, and use that as a reference.

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ysonera
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Registered: ‎02-25-2019

Hierarchy from Questasim...

ysonera_0-1615662309645.png

 

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graces
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Registered: ‎07-16-2008

What hierarchy did you observe in Questasim? From the snapshot, I didn't see 'inst' indeed.

Is the `define specify in a separate header file? Was it compiled correctly?

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ysonera
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The `define is in the same file and the simulator error message is expanding it correctly. There were no errors during compilation of the VHDL design or the SV testbench sources. I did some errors in the compilation of the simulation libraries using the following command:

 

 

compile_simlib -simulator questa -simulator_exec_path {Z:/mentor/questasim/10.7c/Windows/win64} -family zynquplus -language all -library unisim -dir {<redacted>/vivado}

 

 

 

I tried different versions of questasim and Vivado (per https://www.xilinx.com/support/answers/68324.html) to make sure that it wasn't a compatibility issue but I got the same errors (see below). 

 

 

***********************************************************************************************************************
*  Library                                | Language |          Mapped Library Name           | Error(s) | Warning(s) *
*---------------------------------------------------------------------------------------------------------------------*
*  qdma_v3_0_0                            | verilog  | qdma_v3_0_0                            | 0        | 755        *
*---------------------------------------------------------------------------------------------------------------------*
*  processing_system7_vip_v1_0_6          | verilog  | processing_system7_vip_v1_0_6          | 1        | 0          *
*---------------------------------------------------------------------------------------------------------------------*
*  zynq_ultra_ps_e_vip_v1_0_4             | verilog  | zynq_ultra_ps_e_vip_v1_0_4             | 1        | 0          *
*---------------------------------------------------------------------------------------------------------------------*
ERROR: [Vivado 12-5602] compile_simlib failed to compile for questasim with error in 2 libraries (cxl_error.log)
compile_simlib: Time (s): cpu = 00:02:26 ; elapsed = 00:21:17 . Memory (MB): peak = 1394.273 ; gain = 42.520
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.

 

 

 

 

 

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graces
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Registered: ‎07-16-2008

Can you attach cxl_error.log to show the exact error message of the two IP libraries?

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ysonera
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Not sure why but its having issues with 'Could not find the package (axi_vip_pkg)'

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graces
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Registered: ‎07-16-2008

If you see the same error with Questasim 2019.2 (which is the compatible version), it should be caused by something else.

What about IP xilinx_vip? Was it successfully compiled?

Take processing_system7_vip_v1_0_8 for example, the complete log looks like this.

-- Compiling module processing_system7_vip_v1_0_8_arb_wr
-- Compiling module processing_system7_vip_v1_0_8_arb_rd
-- Compiling module processing_system7_vip_v1_0_8_arb_wr_4
-- Compiling module processing_system7_vip_v1_0_8_arb_rd_4
-- Compiling module processing_system7_vip_v1_0_8_arb_hp2_3
-- Compiling module processing_system7_vip_v1_0_8_arb_hp0_1
-- Compiling module processing_system7_vip_v1_0_8_ssw_hp
-- Compiling module processing_system7_vip_v1_0_8_sparse_mem
-- Compiling module processing_system7_vip_v1_0_8_reg_map
-- Compiling module processing_system7_vip_v1_0_8_ocm_mem
-- Compiling module processing_system7_vip_v1_0_8_intr_wr_mem
-- Compiling module processing_system7_vip_v1_0_8_intr_rd_mem
-- Compiling module processing_system7_vip_v1_0_8_fmsw_gp
-- Compiling module processing_system7_vip_v1_0_8_regc
-- Compiling module processing_system7_vip_v1_0_8_ocmc
-- Compiling module processing_system7_vip_v1_0_8_interconnect_model
-- Compiling module processing_system7_vip_v1_0_8_gen_reset
-- Compiling module processing_system7_vip_v1_0_8_gen_clock
-- Compiling module processing_system7_vip_v1_0_8_ddrc
-- Compiling package processing_system7_vip_v1_0_vl_rfs_sv_unit
-- Importing package xilinx_vip.axi_vip_pkg
-- Importing package xilinx_vip.xil_common_vip_pkg
-- Compiling module processing_system7_vip_v1_0_8_axi_slave
-- Compiling module processing_system7_vip_v1_0_8_axi_slave_acp
-- Compiling module processing_system7_vip_v1_0_8_axi_master
-- Compiling module processing_system7_vip_v1_0_8_afi_slave
-- Compiling module processing_system7_vip_v1_0_8

Top level modules:
processing_system7_vip_v1_0_8_intr_wr_mem
processing_system7_vip_v1_0_8

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ysonera
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Although there was no error for xilinx_vip the library folder is empty so I don't think it was successfully compiled. After reading some more Forums I found that I was constraining compile_simlib too much. So I changed the -library option to from 'unisim' to 'all' and the libraries compiled successfully. 

https://forums.xilinx.com/t5/Simulation-and-Verification/Error-about-Compile-Simulation-Libraries-using-cadence-ies-15-2/td-p/1007357

However, I'm still getting the same simulation errors in Questa as before. I'm thinking that may be I'm not compiling all of the Vivado generated sources that are needed for simulation. I'm currently compiling the following sources, where BD_DIR is the path to my Zynq block design.

$BD_DIR/ip/xr_uzev_ps_zynq_ultra_ps_0_0/sim/xr_uzev_ps_zynq_ultra_ps_0_0.sv \
$BD_DIR/ip/xr_uzev_ps_zynq_ultra_ps_0_0/sim/xr_uzev_ps_zynq_ultra_ps_0_0_vip_wrapper.v \
$BD_DIR/ip/xr_uzev_ps_zynq_ultra_ps_0_0/sim/xr_uzev_ps_zynq_ultra_ps_0_0.sv \
$BD_DIR/ip/xr_uzev_ps_zynq_ultra_ps_0_0/sim/xr_uzev_ps_zynq_ultra_ps_0_0_stub.sv \
$BD_DIR/ip/xr_uzev_ps_zynq_ultra_ps_0_0/hdl/zynq_ultra_ps_e_v3_3_1.v \
$BD_DIR/sim/xr_uzev_ps.vhd \
$BD_DIR/hdl/xr_uzev_ps_wrapper.vhd \

 

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graces
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Registered: ‎07-16-2008

Are yourunning simulation in Questasim alone with custom script?  I'd suggest that you run Export > Export Simulation in Vivado IDE to export simulation script for the design targetting Questasim, and use that as a reference.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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ysonera
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I was able to get rid of the hierarchy errors using the Vivado generated sim scripts. However, the compiler still complains about the set_verbosity function, but allows me to continue onto simulation after commenting this line out. There are a few runtime issues that I'm still working through, but I don't think they are related to this. Thanks for the help.

 

# ** Error (suppressible): .../esa_xr_tb.sv(163): (vopt-7063) Failed to find 'set_verbosity' in hierarchical name 'esa_xr_tb.dut.u_xr_uzev_ps.xr_uzev_ps_i.zynq_ultra_ps_0.inst.set_verbosity'.
#         Region: esa_xr_tb
# Optimization failed
# End time: 23:52:06 on Mar 17,2021, Elapsed time: 0:00:02
# Errors: 1, Warnings: 23

 

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