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Visitor
Visitor
3,783 Views
Registered: ‎05-27-2012

warning in ISE(latches maybe generated from incomplete case or if statements)

hello,I keep getting this warning when Isyn the code.how can i remove  warnings?

the parts of code:

process(clk,reset,clk_external)
    variable  i,s,a,c:int ;variable b:integer;
    variable  out_1,Mes_c_to_v,d,Lnew:int;variable col_index_nonzero:integer range 1 to 2304;
    variable multiple_sign,multiple_sign_0,sign_value_i:integer range 1 downto -1;
    begin 
      if reset ='1' then 
        s:=0;i:=0;multiple_sign:=1;
      else
         if (clk 'event and clk='1' )then
          if i=8 then
           i:=1;s:=0;--multiple_sign:=1;
          else
           i:=i+1;
          end if;
			 else
			 i:=i;
         end if;
         s:=col_each_rowblock(i)+sum-1;
         b:=(col_each_rowblock(i)+sum-1)-H(i);
          if b>0 then 
            a:=1;
          else
            a:=0;
          end if;
         case a is 
          when 0 => col_index_nonzero := s;
          when others =>col_index_nonzero:=s-96;
         end case;
		   c:=L(col_index_nonzero);
         if i=index then  
          out_1:=out_min_2;
         else
          out_1:=out_min_1;
         end if;
         Mes_c_to_v:=out_1 * sign_value(i)* sign_each_row ;
        --v<=col_index_nonzero;
        
         d:=c-Mes_c_to_v;
         as(i)<=d;col(i)<=col_index_nonzero;
         abs_Mes_v_to_c(i)<=abs(d);
         if d>= 0 then 
	        sign_value_i:=1;
	      else
	        sign_value_i:=-1;
	      end if;
	      multiple_sign_0:=multiple_sign;
	      multiple_sign:=multiple_sign_0*sign_value_i;
	      sign_each_row_new<=multiple_sign;
	      sign_value_new(i)<=sign_value_i;
	      Mes_v_to_c(i)<=d;
        
        --end if;
      
      end if;
    end process;  

 warnings:

left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <L<2048:2304>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <Mes_v_to_c> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 13-bit latch for signal <as_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <as_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <as_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <sign_each_row_new>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <as_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <as_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <as_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <col_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <col_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <col_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <col_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <col_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <col_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <col_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <col_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <as_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <as_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <$mux0000>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <$mux0001>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <$mux0002>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <$mux0003>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <$mux0004>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <$mux0005>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <$mux0006>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 2-bit latch for signal <$mux0007>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <Mes_v_to_c_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <Mes_v_to_c_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <Mes_v_to_c_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <Mes_v_to_c_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <Mes_v_to_c_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <Mes_v_to_c_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <Mes_v_to_c_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <Mes_v_to_c_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <abs_Mes_v_to_c_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <abs_Mes_v_to_c_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <abs_Mes_v_to_c_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <abs_Mes_v_to_c_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <abs_Mes_v_to_c_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <abs_Mes_v_to_c_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <abs_Mes_v_to_c_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 13-bit latch for signal <abs_Mes_v_to_c_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

 


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Highlighted
Instructor
Instructor
3,782 Views
Registered: ‎07-21-2009

Re: warning in ISE(latches maybe generated from incomplete case or if statements)

Several coding error in here (of course).  Note:  I am not a VHDL user, I am only addressing the errors so grievous that even a Verilog user can detect them.

 

#1

process(clk,reset,clk_external)

 

This defines a clocked process.  Is it not true that the only signals belonging in the sensitivity list of a clocked process are the clock and (if any) asynchronous set/reset?  If so, then why is clk_external  in the process sensitivity list?

 

 

#2

if reset ='1' then
   s:=0;i:=0;multiple_sign:=1;
else
   if (clk 'event and clk='1' )then

     ...

     <some code>

     ...
   else

 

The first IF-THEN defines the async reset/set behaviour.

 

The second IF-THEN is the preamble for all the synchronous logic of the process.  All of the clocked (synchronous) logic immediately follows this second IF-THEN.  After a few lines of code, an ELSE is encountered.  The END IF which follows the ELSE statement effectively ends the clocked process.

 

The ELSE-END IF is followed with 10s of lines of code, none of which falls within the VHDL constructs of synchronous clocked logic, as I understand VHDL.  Hence the abundance of error messages from the synthesiser.

 

Either the IF-THEN-ELSE-END IF construct is mangled, or there are 10s of lines of code which need to reside within a properly constructed clocked or combinatorial process.

 

So...  clean up your code.  It could very well be that my understanding of VHDL structure is entirely mistaken, in which case I profusely apologise and wish to be corrected.

 

Aside from all this, you also have a few undefined (undeclared) signals in your code.

 

Based on this thread and your most recent previous thread, you should consider a formal training course in the use of VHDL.

 

-- Bob Elkind

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