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d4223738
Adventurer
Adventurer
7,271 Views
Registered: ‎04-18-2015

what is the difference between 4'b0000 and 0000?

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Hi,

 

I am a beginner of SystemVerilog. I am doing a very simple design, however, during the simulation in ModelSim,

 

whenever the input = 4'b(any 4bit value), e.g. input = 4'b0000, the output is correct.

 

whenever the input = (a 4 bit value), e.g. input = 0000, the output is incorrect.

 

Anyone could tell me why?

 

Best wishes,

Lei

 

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srimaye
Xilinx Employee
Xilinx Employee
10,987 Views
Registered: ‎09-25-2014

Hi @d4223738,

 

When you are assigning as input = 4'b(any 4bit value), it takes a 4 bit binary value. When you are assigning as the input = (a 4 bit value), it takes as a decimal value. For example :

for in1 = 4'b1111 , the value in binary is 000000000000000000000000000001111

for in1 = 1111 , the value in binary is 000000000000000000000010001010111

 

Thanks,

Srimayee

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srimaye
Xilinx Employee
Xilinx Employee
10,988 Views
Registered: ‎09-25-2014

Hi @d4223738,

 

When you are assigning as input = 4'b(any 4bit value), it takes a 4 bit binary value. When you are assigning as the input = (a 4 bit value), it takes as a decimal value. For example :

for in1 = 4'b1111 , the value in binary is 000000000000000000000000000001111

for in1 = 1111 , the value in binary is 000000000000000000000010001010111

 

Thanks,

Srimayee

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d4223738
Adventurer
Adventurer
7,252 Views
Registered: ‎04-18-2015

Hi,

 

Thank you for the reply.

 

In my case,  both cases are all binary value. Please see the photo attached.

IMG_20161129_104004.jpg
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balkris
Xilinx Employee
Xilinx Employee
7,239 Views
Registered: ‎08-01-2008
4 bit binary should be represented by 4'b000 , 0000 may not give correct results . For both are zero so it should behave same way however you need to check synthesis design.

This may be expected behavior . You may try running with some more input values
Thanks and Regards
Balkrishan
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d4223738
Adventurer
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7,236 Views
Registered: ‎04-18-2015

Hi @srimaye@balkris

 

Thank you for the reply.

 

In my case,  both cases are all binary value. Please see the photo attached.

 

IMG_20161129_104004.jpg
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avrumw
Guide
Guide
7,198 Views
Registered: ‎01-23-2009

both cases are all binary value

 

That's exactly the point. Verilog supports constants in different bases - binary, octal, decimal and hexadecimal. With no specification the default is decimal.

 

So without a base specification

 

input = 1111;

 

This is interpreted as a decimal number - one thousand, one hundred and eleven.

 

With the base specification

 

input = 4'b1111;

 

This is interpreted as a binary number - the binary number 1111, which is the equivalent of 15 in decimal.

 

Avrum

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