cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
146 Views
Registered: ‎03-17-2020

why is the divided_clk line here showing Z across the simulation?

Hello, I am experimenting with a user selectable clock divider module, or at least trying to. I can simulate and generate a fixed configuration, with a test bench, but why wouldn't divided_clk show any activity, other than Z? The loop counter obviously is working, (0..49, then back to 0), and that is where I would have expected a flip of the divided_clock, at least that was what I was hoping to achieve.

If I place clock_divider in the testbench instantiation statement, then clock_divider output is zero. It doesn't actually change, even at the 49th iteration of counter_value. I am trying to divide a 100 MHz clock to a 1MHz clock in simulation.

Where should I be focusing attention? (using Vivado 2019.2 WebPack)

test.v (module)

`timescale 1ns / 1ps
// key === button
module test(
	sys_clk,     // will use onboard 100 MHz clock
	key,         //buttons 1,2
	led,         //indicator LED
	divided_clk  //reduced frequency clk
	);
	input wire sys_clk;          //to be connected to board clk source (assume = 100 MHz onboard clock chip)
	input wire [1:0] key;        //two independent button input
	output reg led;             //led output under button control
	output reg divided_clk; //divided clock line
     		
  	localparam div_value = 49; // 1 MHz (we can make this different each iteration)
	// div_value = ((sys_clk freq)/(2 * desired freq))-1.
	// 1 Hz, from 100 MHz, div_value = 49999999
	// 10 Hz, from 100 MHz, div_value = 4999999
	// 100 Hz, from 100 MHz, div_value = 499999
	// 1kHz, from 100 MHz, div_value =    49999
	// 10kHz, from 100 MHz, div_value =    4999
	// 100kHz, from 100 MHz, div_value =    499
	// 1MHz, from 100 MHz, div_value =       49
	// div_value = [(f_osc / (2 * f_req))-1]
	
	integer counter_value = 0;
	
	// light LED if key[0] and key[1] are pressed together
	wire flag = key[0] & key[1];
	always @(posedge sys_clk)begin
		if(flag)
			led <= 1'b1;
		else
			led <= 1'b0;
	end
 
	// divide the clk per div_value table above for required f.
    always@ (posedge sys_clk)                   //sensitivity
	begin
		if (counter_value == div_value)
			counter_value = 32'b0;                  //reset counter_value
		else
			counter_value <= counter_value + 1; // count up to div_value
		
	//divide the sys_clk
		if (counter_value == div_value)
			divided_clk <= ~divided_clk; //flip the signal
		else
			divided_clk <= divided_clk; // store the value
	end
	
initial begin
	divided_clk <= 0;
end
	
endmodule

test_tb.v (testbench)

`timescale 1ns / 1ps

module test_tb();
//---------------------------------------------------------
// inputs to the DUT are reg type
reg clk;
reg [1:0] key_in;

//--------------------------------------------------------
// outputs from the DUT are wire type
wire led;
wire divided_clk;

//---------------------------------------------------------
// instantiate the Device Under Test (DUT)
// using named instantiation
// The signals with a dot in front of them are 
// the names for the signals inside the instantiated  module
// while the wire or reg they connect to IN THE TEST BENCH
// is next to the signal in parenthesis
      
test uut_test(
              .sys_clk(clk),
              .key(key_in),
              .led(led)
//			  .divided_clk(divided_clk)
        );      
initial //initial block executes only once
begin 
    clk  = 1'b0;
    key_in = 2'b11;
	
	// binary sw sequence 0,1,2,3,2,1,0,1,2,3,0
    #30 key_in = 2'b00;
    #30 key_in = 2'b01;
    #30 key_in = 2'b10;
    #30 key_in = 2'b11;
	#30 key_in = 2'b10;  
    #30 key_in = 2'b01;
    #30 key_in = 2'b00;
    #20 key_in = 2'b01;
    #30 key_in = 2'b10;
    #20 key_in = 2'b11;
    #30 key_in = 2'b00; 
end        
always #5 clk = ~clk;       // 5nS x 2 = 10nS period = 100 MHz clock
endmodule






 

Capture.JPG
0 Kudos
1 Reply
Highlighted
Observer
Observer
112 Views
Registered: ‎03-17-2020

solved the problem by rearranging and modifying the always block.
0 Kudos