cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sraza
Explorer
Explorer
2,529 Views
Registered: ‎03-13-2012

why only input ports dump in ISIM vcd in following?

Jump to solution

hello every one 

 

I need to catch few signals for VCD so I learn how to dump vcd files in ISIM, so I get to know about statements but the thing is when I applied them I only got the input ports as dump file. I tried it a few times with same result every time.

 

Folowwing is my code which shows the output is cntr, but I cannot get it in the vcd

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cnt is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           cntr : out  integer range 0 to 7;
           x : in  STD_LOGIC);
end cnt;

architecture Behavioral of cnt is

signal cntr_s : integer range 0 to 7;
begin
cntr <= cntr_s;

process(clk, rst)
begin
if(rst = '1') then
	cntr_s <= 0;
	elsif(rising_edge(clk)) then
	cntr_s <= cntr_s + 1;

end if;
end process;

end Behavioral;

 following are the vcd commands I issued over ISIM

 

ISim> vcd dumpfile dump_main.vcd
ISim> vcd dumpvars -m /UUT -l 0
ISim> run 1000 ns
..
..
ISim> vcd dumpflush

 Note that I did it without using -l operator as well

 

The dump file is attached

 

Jaffry

Tags (2)
0 Kudos
Reply
1 Solution

Accepted Solutions
graces
Moderator
Moderator
3,084 Views
Registered: ‎07-16-2008

It looks that the issue has something to do with the cntr declared as integer output.

I tried to replace it with std_logic_vector type and the vcd dump looks fine.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;

entity test is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
--           cntr : out  integer range 0 to 7;
           cntr : out  std_logic_vector(2 downto 0);
           x : in  STD_LOGIC);
end test;

architecture Behavioral of test is

signal cntr_s : integer range 0 to 7;
begin
cntr <= CONV_STD_LOGIC_VECTOR (cntr_s, 3);

process(clk, rst)
begin
if(rst = '1') then
	cntr_s <= 0;
	elsif(rising_edge(clk)) then
	cntr_s <= cntr_s + 1;

end if;
end process;

end Behavioral;

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

1 Reply
graces
Moderator
Moderator
3,085 Views
Registered: ‎07-16-2008

It looks that the issue has something to do with the cntr declared as integer output.

I tried to replace it with std_logic_vector type and the vcd dump looks fine.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;

entity test is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
--           cntr : out  integer range 0 to 7;
           cntr : out  std_logic_vector(2 downto 0);
           x : in  STD_LOGIC);
end test;

architecture Behavioral of test is

signal cntr_s : integer range 0 to 7;
begin
cntr <= CONV_STD_LOGIC_VECTOR (cntr_s, 3);

process(clk, rst)
begin
if(rst = '1') then
	cntr_s <= 0;
	elsif(rising_edge(clk)) then
	cntr_s <= cntr_s + 1;

end if;
end process;

end Behavioral;

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post