A netlist simulation has to simulate every register and LUT individually. The RTL code may contain a single line that coverts into hundreds of gates and registers.
Netlist simulation is mostly avoided now. With good functional testbenches at the RTL level and full timing specs, most people just go from RTL directly to the board. You can run far more data through the real design than a simulation (particularly a netlist).
I havent done a single netlist simulation in 15 years.