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294 Views
Registered: ‎01-07-2020

why post synthesis simulation is very slow

I am using Vivado 2019.2 and run my RTL code.

The behavioral simulation is fine. However post synthesis functional simulation take  very long time

I try to reduce output port but still the same 

跑超久.png

 

 

per iteration computation spend 25 mins,  total have to run 300 times.

 

Thanks

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Scholar
Scholar
284 Views
Registered: ‎08-01-2012

Yes, this is expected.

A netlist simulation has to simulate every register and LUT individually. The RTL code may contain a single line that coverts into hundreds of gates and registers.

Netlist simulation is mostly avoided now. With good functional testbenches at the RTL level and full timing specs, most people just go from RTL directly to the board. You can run far more data through the real design than a simulation (particularly a netlist).

I havent done a single netlist simulation in 15 years.