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mofana
Visitor
Visitor
6,701 Views
Registered: ‎05-02-2016

xelab error in linking C files to systemverilog

Hi folks,

 

I have the C model of a component in our system, and want to include it in my test bench in Vivado. Following is the C file (model_main.c) that I use for modeling the component:

 

 

#include "COMPONENT_MODEL.h"
#include "svdpi.h"

DPI_DLLESPEC
void model_step(const double in1, const double in2, double *out1)
{
	static COMPONENT_MODEL_DATA *myComponent;
	static bool firstTime = true;
	if (firstTime){
		myComponent = Generate_Component();
		Component_initialize(myComponent);
		firstTime = false;
	}
	//set inputs...
	Component_step(myComponent);
	//set output
}

And here is my model_wrapper.sv file using DPI:

 

 

module model_wrapper(
    input   int in1,
    input   int in2,
    output  int out1
    );
  real out_1;
  real in_1, in_2;
  import "DPI-C" pure function void model_step(input real in1, input real in2, output real out1);
  
  always
  begin
    #1000;
    in_1  = (in1   * 1.00)/(2.0**24);
    in_2  = (in2 * 1.00)/(2.0**24);
    model_step(in_1, in_2, out_1);
    out1 = out_1 * 2**24;
  end
endmodu

 

I successfully compile and link the model_main.c, and create the dpi.a file. Then I use the xelab to link it to the model_wrapper.sv, where I encounter this error:

Running: c:/Xilinx/Vivado/2015.2/bin/unwrapped/win64.o/xelab.exe -svlog model_wrapper.sv -sv_lib dpi
Multi-threading is on. Using 2 slave threads.
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "model_wrapper.sv" into library work
INFO: [VRFC 10-311] analyzing module model_wrapper
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.model_wrapper
Waiting for 3 sub-compilation(s) to finish...
0 sub-compilation(s) remaining...
xsim.dir/work.model_wrapper/obj/xsim_3.win64.obj:xsim_3.c:(.text+0x46): undefined reference to `model_step'
collect2: ld returned 1 exit status
ERROR: [XSIM 43-3238] Failed to link the design.

So, basically, it cannot find a reference to model_step function, which I don't know why. Then, I removed any input/output of the model_step function, as follows:

in model_main.c:
void model_step() //(const double in1, const double in2, double *out1)

in model_wrapper.sv:
import "DPI-C" pure function void model_step(); //(input real in1, input real in2, output real out1);

Now, the xelab still fails to link with following errors:

dpi.a(model_main.win64.obj):model_main.c:(.text+0xe): undefined reference to `Generate_Component'
dpi.a(model_main.win64.obj):model_main.c:(.text+0x1d): undefined reference to `Component_initialize'
dpi.a(model_main.win64.obj):model_main.c:(.text+0x53): undefined reference to `Component_step'
collect2: ld returned 1 exit status
ERROR: [XSIM 43-3238] Failed to link the design.
  

My understanding is that there should be some issue with passing variables between functions. But what, and why? Please help me in fixing this out.

 

Thanks,

 

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6 Replies
balkris
Xilinx Employee
Xilinx Employee
6,692 Views
Registered: ‎08-01-2008

check this post
https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-ERROR-XSIM-43-3238-Failed-to-link-the-design/td-p/411281

 

https://forums.xilinx.com/t5/Welcome-Join/Vivado-2015-4-XSIM-43-3238-Failed-to-link-the-design/td-p/705146
https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-2016-1-simulation-quot-Failed-to-link-design-quot/td-p/698527


this ARs may help
http://www.xilinx.com/support/answers/67272.html

Thanks and Regards
Balkrishan
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mofana
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6,684 Views
Registered: ‎05-02-2016

Thank you @balkris,

Well, I don't have problem in running Vivado at all. I am using Vivado 2015.2 and I simulate my verilog/VHDL sources finely. The issue arises when I want to call C files from my systemverilog code.

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balkris
Xilinx Employee
Xilinx Employee
6,681 Views
Registered: ‎08-01-2008

you may share your test case . Let me check if any such known issue with systemverilog
Thanks and Regards
Balkrishan
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srimaye
Xilinx Employee
Xilinx Employee
6,672 Views
Registered: ‎09-25-2014

Hi @mofana ,

 

Can you send the COMPONENT_MODEL.h used in the c function?

 

Thanks,

Srimayee

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mofana
Visitor
Visitor
6,668 Views
Registered: ‎05-02-2016

@srimaye@balkris

Unfortunately, I cannot share the code, due to NDA, and IP cases. Though, I compiled and simulated the C code in Visual studio with no problem.

 

I'll update here if I found some hints to the root cause, or found the fix.

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555 Views
Registered: ‎07-23-2019

I can do what you are describing here when I compile, elaborate and start Vivado in batch mode.
But then I face another issue:

ERROR: [XSIM 43-4100] "/wrk/2018.2/continuous/2018_06_14_2258646/data/secureip/gtpe2_channel/gtpe2_channel_001.vp" Line 3. Module GTPE2_CHANNEL_WRAP(ACJTAG_DEBUG_MODE="0",ACJTAG_MODE="0",ACJTAG_RESET="0",ADAPT_CFG0="00000000000000000000",ALIGN_COMMA_DOUBLE="FALSE",ALIGN_COMMA_ENABLE="1111111111",ALIGN_COMMA_WORD=1,ALIGN_MCOMMA_DET="TRUE",ALIGN_MCOMMA_VALUE="1010000011",ALIGN_PCOMMA_DET="TRUE",ALIGN_PCOMMA_VALUE="0101111100",CBCC_DATA_SOURCE_SEL="DECODED",CFOK_CFG="1001001000000000000000001000000111010000000",CFOK_CFG2="0100000",CFOK_CFG3="0100000",CFOK_CFG4="0",CFOK_CFG5="00",CFOK_CFG6="0000",CHAN_BOND_KEEP_ALIGN="FALSE",CHAN_BOND_MAX_SKEW=1,CHAN_BOND_SEQ_1_1="0000000000",CHAN_BOND_SEQ_1_2="0000000000",CHAN_BOND_SEQ_1_3="0000000000",CHAN_BOND_SEQ_1_4="0000000000",CHAN_BOND_SEQ_1_ENABLE="1111",CHAN_BOND_SEQ_2_1="0000000000",CHAN_BOND_SEQ_2_2="0000000000",CHAN_BOND_SEQ_2_3="0000000000",CHAN_BOND_SEQ_2_4="0000000000",CHAN_BOND_SEQ_2_ENABLE="1111",CHAN_BOND_SEQ_2_USE="FALSE",CHAN_BOND_SEQ_LEN=1,CLK_COMMON_SWING="0",CLK_CORRECT_USE="FALSE",CLK_COR_KEEP_IDLE="FALSE",CLK_COR_MAX_LAT=9,CLK_COR_MIN_LAT=7,CLK_COR_PRECEDENCE="TRUE",CLK_COR_REPEAT_WAIT=0,CLK_COR_SEQ_1_1="0100000000",CLK_COR_SEQ_1_2="0000000000",CLK_COR_SEQ_1_3="0000000000",CLK_COR_SEQ_1_4="0000000000",CLK_COR_SEQ_1_ENABLE="1111",CLK_COR_SEQ_2_1="0100000000",CLK_COR_SEQ_2_2="0000000000",CLK_COR_SEQ_2_3="0000000000",CLK_COR_SEQ_2_4="0000000000",CLK_COR_SEQ_2_ENABLE="1111",CLK_COR_SEQ_2_USE="FALSE",CLK_COR_SEQ_LEN=1,DEC_MCOMMA_DETECT="TRUE",DEC_PCOMMA_DETECT="TRUE",DEC_VALID_COMMA_ONLY="TRUE",DMONITOR_CFG="000a00",ES_CLK_PHASE_SEL="0",ES_CONTROL="000000",ES_ERRDET_EN="FALSE",ES_EYE_SCAN_EN="FALSE",ES_HORZ_OFFSET="010",ES_PMA_CFG="0000000000",ES_PRESCALE="00000",ES_QUALIFIER="00000000000000000000",ES_QUAL_MASK="00000000000000000000",ES_SDATA_MASK="00000000000000000000",ES_VERT_OFFSET="000000000",FTS_DESKEW_SEQ_ENABLE="1111",FTS_LANE_DESKEW_CFG="1111",FTS_LANE_DESKEW_EN="FALSE",GEARBOX_MODE="000",LOOPBACK_CFG="0",OUTREFCLK_SEL_INV="11",PCS_PCIE_EN="FALSE",PCS_RSVD_ATTR="000000000100",PD_TRANS_TIME_FROM_P2="03c",PD_TRANS_TIME_NONE_P2="3c",PD_TRANS_TIME_TO_P2="64",PMA_LOOPBACK_CFG="0",PMA_RSV="00000333",PMA_RSV2="00002040",PMA_RSV3="00",PMA_RSV4="0000",PMA_RSV5="0",PMA_RSV6="0",PMA_RSV7="0",RXBUFRESET_TIME="00001",RXBUF_ADDR_MODE="FAST",RXBUF_EIDLE_HI_CNT="1000",RXBUF_EIDLE_LO_CNT="0000",RXBUF_EN="FALSE",RXBUF_RESET_ON_CB_CHANGE="TRUE",RXBUF_RESET_ON_COMMAALIGN="FALSE",RXBUF_RESET_ON_EIDLE="FALSE",RXBUF_RESET_ON_RATE_CHANGE="TRUE",RXBUF_THRESH_OVFLW=61,RXBUF_THRESH_OVRD="FALSE",RXBUF_THRESH_UNDFLW=4,RXCDRFREQRESET_TIME="00001",RXCDRPHRESET_TIME="00001",RXCDR_CFG="0001107fe206021081010",RXCDR_FR_RESET_ON_EIDLE="0",RXCDR_HOLD_DURING_EIDLE="0",RXCDR_LOCK_CFG="001001",RXCDR_PH_RESET_ON_EIDLE="0",RXDLY_CFG="001f",RXDLY_LCFG="030",RXDLY_TAP_CFG="0000",RXGEARBOX_EN="FALSE",RXISCANRESET_TIME="00001",RXLPMRESET_TIME="0001111",RXLPM_BIAS_STARTUP_DISABLE="0",RXLPM_CFG="0110",RXLPM_CFG1="0",RXLPM_CM_CFG="0",RXLPM_GC_CFG="111100010",RXLPM_GC_CFG2="001",RXLPM_HF_CFG="00001111110000",RXLPM_HF_CFG2="01010",RXLPM_HF_CFG3="0000",RXLPM_HOLD_DURING_EIDLE="0",RXLPM_INCM_CFG="1",RXLPM_IPCM_CFG="0",RXLPM_LF_CFG="000000001111110000",RXLPM_LF_CFG2="01010",RXLPM_OSINT_CFG="100",RXOOB_CFG="0000110",RXOOB_CLK_CFG="FABRIC",RXOSCALRESET_TIME="00011",RXOSCALRESET_TIMEOUT="00000",RXOUT_DIV=2,RXPCSRESET_TIME="00001",RXPHDLY_CFG="084020",RXPH_CFG="c00002",RXPH_MONITOR_SEL="00000",RXPI_CFG0="000",RXPI_CFG1="1",RXPI_CFG2="1",RXPMARESET_TIME="00011",RXPRBS_ERR_LOOPBACK="0",RXSLIDE_AUTO_WAIT=7,RXSLIDE_MODE="PCS",RXSYNC_MULTILANE="0",RXSYNC_OVRD="0",RXSYNC_SKIP_DA="0",RX_BIAS_CFG="0000111100110011",RX_BUFFER_CFG="000000",RX_CLK25_DIV=4,RX_CLKMUX_EN="1",RX_CM_SEL="00",RX_CM_TRIM="0000",RX_DATA_WIDTH=20,RX_DDI_SEL="000000",RX_DEBUG_CFG="00000000000000",RX_DEFER_RESET_BUF_EN="TRUE",RX_DISPERR_SEQ_MATCH="TRUE",RX_OS_CFG="0000010000000",RX_SIG_VALID_DLY=10,RX_XCLK_SEL="RXUSR",SAS_MAX_COM=64,SAS_MIN_COM=36,SATA_BURST_SEQ_LEN="0101",SATA_BURST_VAL="100",SATA_EIDLE_VAL="100",SATA_MAX_BURST=8,SATA_MAX_INIT=21,SATA_MAX_WAKE=7,SATA_MIN_BURST=4,SATA_MIN_INIT=12,SATA_MIN_WAKE=4,SATA_PLL_CFG="VCO_3000MHZ",SHOW_REALIGN_COMMA="TRUE",SIM_RECEIVER_DETECT_PASS="TRUE",SIM_RESET_SPEEDUP="TRUE",SIM_TX_EIDLE_DRIVE_LEVEL="X",SIM_VERSION="2.0",TERM_RCAL_CFG="100001000010000",TERM_RCAL_OVRD="000",TRANS_TIME_RATE="0e",TST_RSV="00000000",TXBUF_EN="TRUE",TXBUF_RESET_ON_RATE_CHANGE="TRUE",TXDLY_CFG="001f",TXDLY_LCFG="030",TXDLY_TAP_CFG="0000",TXGEARBOX_EN="FALSE",TXOOB_CFG="0",TXOUT_DIV=2,TXPCSRESET_TIME="00001",TXPHDLY_CFG="084020",TXPH_CFG="0780",TXPH_MONITOR_SEL="00000",TXPI_CFG0="00",TXPI_CFG1="00",TXPI_CFG2="00",TXPI_CFG3="0",TXPI_CFG4="0",TXPI_CFG5="000",TXPI_GREY_SEL="0",TXPI_INVSTROBE_SEL="0",TXPI_PPMCLK_SEL="TXUSRCLK2",TXPI_PPM_CFG="00000000",TXPI_SYNFREQ_PPM="001",TXPMARESET_TIME="00001",TXSYNC_MULTILANE="0",TXSYNC_OVRD="0",TXSYNC_SKIP_DA="0",TX_CLK25_DIV=4,TX_CLKMUX_EN="1",TX_DATA_WIDTH=20,TX_DEEMPH0="000000",TX_DEEMPH1="000000",TX_DRIVE_MODE="DIRECT",TX_EIDLE_ASSERT_DELAY="110",TX_EIDLE_DEASSERT_DELAY="100",TX_LOOPBACK_DRIVE_HIZ="FALSE",TX_MAINCURSOR_SEL="0",TX_MARGIN_FULL_0="1001110",TX_MARGIN_FULL_1="1001001",TX_MARGIN_FULL_2="1000101",TX_MARGIN_FULL_3="1000010",TX_MARGIN_FULL_4="1000000",TX_MARGIN_LOW_0="1000110",TX_MARGIN_LOW_1="1000100",TX_MARGIN_LOW_2="1000010",TX_MARGIN_LOW_3="1000000",TX_MARGIN_LOW_4="1000000",TX_PREDRIVER_MODE="0",TX_RXDETECT_CFG="1832",TX_RXDETECT_REF="100",TX_XCLK_SEL="TXOUT",UCODEER_CLR="0",USE_PCS_CLK_PHASE_SEL="0") has a timescale but at least one module in design doesn't have timescale.

Anyone having an idea how to solve this?

When I define Vivado Project in GUI environement, I build the Design Hiearchy manually and I do now have problems with SecureIP, but I can not link C to SysVerilog.

When I run in batch mode, I can link C to SysVerilog but I have problems binding SecureIP blocks to my design.
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