09-09-2020 11:46 AM
I've been using Vivado for VHDL development for a few years now. Right now I'm trying to simulate a piece of VHDL that includes some Xilinx IP's (DDS, clocking wizard and Cordic) I use the DDS to generate a sine/cosine, then I have a couple of MAC's to perform phase-sensitive detection on a file of generated input data, and the cordic then generates an amplitude/phase on the MAC's output. I run the simulation fine for the firs msec, but when it tries to go over the 1ms mark I get an error:
ERROR: Index 48 out of bound 0 to 8
Time: 998818750 ps Iteration: 5 Process: /TestLockIn/tip_detector_1/adc_lockin_detector/AmplitudePhase_Cordic/U0/i_synth/i_synth/gen_cordic/input_stage/gen_rotation/gen_rot_xy/gen_x_min_y/inst/i_baseblox/i_baseblox_addsub/no_pipelining/the_addsub/i_lut6/i_lut6_addsub/i_simple_model/i_no_bypass/line__3179
So, if I'm reading this correctly, the error seems to be in the Cordic IP. The c_addsub_v12_0_vh_rfs.vhd is actually encrypted, so I can't really look at what's happening inside. I guess my question is, is this actually an error on the Xilinx IP simulation, or could still be an error on my side. BTW, the synthesis and implementation work. I had been using Vivado 2016.4, but I tried 2019.2 and I get the same error.
09-10-2020 03:26 AM
Can you see any of the internal waveform. Without any code its going to be nearly impossible to track down an overflow during simulation.
Synthesis will likely work as the indexing signal will just be a 4 bit signal (0 to 8 need 4 bits) and can just overflow as needed.
09-10-2020 08:47 AM
It's probably an error where the design probably doesn't check for max value during increment, and if at max value, setting the index back to 0. But we cannot tell since it is encrypted, so kudos for submitting this. Hopefully somebody will stop by and take a look at the unencrypted code and look for offending lack of overflow check.
09-10-2020 10:11 AM
Thank you both for your answer,
Let me see if I can reduce the code to something self-contained that I can post. One thing I did yesterday was to just comment out the instantiation of the Cordic IP, and that allowed the simulation to run to the end, with, of course, no useful output.