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Newbie vitjka
Newbie
166 Views
Registered: ‎11-02-2018

xsim fails to include signals used in procedures into sensitivity list of the process(all)

Hi, this issue is still present in vivado 2019.1, here is the testcase:

library ieee;
use ieee.std_logic_1164.all;

entity process_all_tb is end entity process_all_tb;
architecture simul of process_all_tb is
signal clock: std_ulogic := '0';
signal ff_not_working: std_ulogic := '0';
signal ff_working: std_ulogic := '0';
begin
clock <= transport not clock after 5 ns;
-- xsim fails to include signals used in procedures into sensitivity list of the process(all):
process(all)
procedure flip_flop is
begin
if clock = '1' then
ff_not_working <= '0';
else
ff_not_working <= '1';
end if;
end procedure;
begin
flip_flop;
end process;
-- it works correctly here
process(all)
begin
if clock = '1' then
ff_working <= '0';
else
ff_working <= '1';
end if;
end process;
end architecture simul;

 

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1 Reply
Moderator
Moderator
122 Views
Registered: ‎04-24-2013

Re: xsim fails to include signals used in procedures into sensitivity list of the process(all)

Hi @vitjka ,

Thank you for the test code, I have run it in the latest version of the tools and can see that the signal in the procedure doesn't change as you would expect.
I also checked it against Questa and can see the signal changing.

I will create a Change Request to get this issue looked at and hopefully fixed in a future release of the tools.

Best Regards
Aidan

 

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