Run as:
$ xvlog vivado3.v
$ xelab work.top
$ xsim -R work.top
This produces the expected result on Vivado 2018.1, but fails on
2019.2/3 and 2020.1. It passes on all the big 3, and various other
simulators. See also https://www.edaplayground.com/x/4peH. The failure
means that current Vivados can't realistically be used for timing
simulations.
Note that I've been sitting on this particular bug for months, again
trying to find someone at Xilinx who is actually interested in bug
reports, before, as usual, resorting to the forums.
The expected output is:
0 A1: 0; B1: x
30 A1: 0; B1: 1
62 A1: 1; B1: 1
79 A1: 1; B1: x
92 A1: 1; B1: 0
Vivado 2019.3 instead gives this output:
0 A1: 0; B1: x
1 A1: 0; B1: 1
17 A1: 0; B1: x
30 A1: 0; B1: 1
62 A1: 1; B1: 1
63 A1: 1; B1: 0
79 A1: 1; B1: x
92 A1: 1; B1: 0
The waveform display is basically more-or-less random. You can
persuade 2019.3 to give the correct answer by commenting out line 49,
which is an instantiation of an unused inverter ('i2'), so it's
clearly a bug.
`timescale 100ps/100ps
module inverter
#(parameter tAH = 1, tAD = 2)
(input A, output B);
wire Ad1, Ad2;
reg AX = 0;
integer hold_delay, output_delay;
// inertial delay to set the new value of the output
assign
#(((tAD > 0))? tAD-1:tAD)
Ad1 = A;
// force the output to X after the hold time, up to the
// output delay time
assign Ad2 = (AX === 1'b1)? 1'bx : Ad1;
// derive a timing window over which the output will be forced to X
always @(A)
begin
if(tAD == 0) // zero-delay sims require special treatment
AX = 0;
else begin
hold_delay = tAH;
output_delay = tAD - tAH - 1;
#(hold_delay) AX = 1;
#(output_delay) AX = 0;
end
end
// implement the logic
assign B = !Ad2;
endmodule
module top;
reg A1, A2;
wire B1, B2;
initial begin
$monitor("%0t A1: %0d; B1: %0d", $time, A1, B1);
A1 = 1'b0;
#62 A1 = 1'b1;
#100 $finish;
end
inverter #(17, 31) i1(A1, B1);
inverter #(17, 30) i2(A2, B2); // comment out to get the right answer
endmodule
