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Explorer
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Registered: ‎07-28-2010

100 MHZ counter design in SPARTAN 3

Hi

 

I am trying to investigate the  worst case counting error introduced by SPARTAN 3  as a function of counter size  at 100 MHz. In order to calculate the error I may need a stable high resolution clock like ceasium or rubidium.

 

What I have used is

 

 two boards each having  Spartan 3.

 

I have attached the results

 

Looking forward to hear your comments.

 

Regards

 

Faisal

 

 

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Registered: ‎01-03-2008

Re: 100 MHZ counter design in SPARTAN 3

If the ISE Timing Analyzer reports that the counter will run at 100 MHz or faster the it will work without any error at 100 MHz.

 

Why do you think that there would be any errors in the counter?

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Re: 100 MHZ counter design in SPARTAN 3

Thanks mcgett

 

Why do you think that there would be any errors in the counter?

 

As the counter bit increases drift between the boards  increases. Here the drift is actually error in counting. If there is no counting error both traces  should be aligned.

 

Faisal

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Registered: ‎07-21-2009

Re: 100 MHZ counter design in SPARTAN 3

If there is no counting error both traces should be aligned.

Do you mean to say

If there is no counting error both counters should match.

You are correct if both counters share the same clock and reset signal.

 

Faisal, you need to be more specific what you mean by "counting error".  I suspect the term "accumulated timebase mismatch or drift" might describe your question better than "counting error".

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

You have two boards each with a unique clock source. The difference in the counter value is due to a ppm differences in your two clock sources, not due to a counter error.

Counters can't have inherent errors in them it would make every design unstable.
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Re: 100 MHZ counter design in SPARTAN 3

Thanks

 

you need to be more specific what you mean by "counting error".  I suspect the term "accumulated timebase mismatch or drift" might describe your question better than "counting error".


Yes  I mean it . I applogize .

 

 

You have two boards each with a unique clock source. The difference in the counter value is due to a ppm differences in your two clock sources, not due to a counter error.

 

Yes I agree. Clock sources in bothe boards  are unique. They are same in frequency  , frequency stability , age and from the same manufacturer. Of course they are not 100 percent same.  If the drift is due to ppm differences  ,then this will be seen in all the plots. But it woudn't. Now Lets assume  that relative error between two oscillators are zero since they are identical in all repects ,the remaining error source is only the FPGA itself I guess. Please correct me.

 

Kind Regards


Faisal

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Registered: ‎07-21-2009

Re: 100 MHZ counter design in SPARTAN 3

Now Lets assume  that relative error between two oscillators are zero since they are identical in all repects ,the remaining error source is only the FPGA itself I guess. Please correct me.

This would be true only if the two FPGA timebases are phase-aligned, and the counter reset signals are also clock-period aligned.  They should reset to the same value in the same clock cycle, and should count uniformly at each clock cycle.

 

If identical counters count differently in one FPGA than another, from one clock cycle to the next, any FPGA design using a counter would be inherently unreliable.  Is this the problem you are trying to describe or prove?

 

I don't think this premise is valid.  If you agree that FPGA counters do work as intended, and you are seeing counter mismatches between FPGAs, there should be a logical explanation for the mismatches.

 

If you want to test your premise, then you only need a single FPGA.  A single FPGA with two identical counters would represent the same case as two FPGAs with perfectly matched oscillators and reset inputs.  If you compare two identical counters in a single FPGA, do they match or not?

 

- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

Your assumption that the relative error between the two clocks is zero because the devices have the same specifications is wrong. These devices have a lower PPM variance, but it isn't zero. The only way to have a zero PPM is to use the same.
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Re: 100 MHZ counter design in SPARTAN 3

Hi

 

well I've scanned your report pdf, 

 

your conclusions on why the edges jitter / drift .

 

 

(i). Oscillator
(ii). FPGA and rest of the circuitry
(iii). Oscilloscope
Well, I hope you get that proof read before you submit it...
Can I suggest that you just put one scope probe on each of the two clocks on the boards,
   and look how the clocks seem on the display.
   you will see that the two clocks are
     a) different frequencies
     b) arbitery phase
     c) different jitters.
can you quantify this in your report ?
how do you think these effects affect your counter measurments ?

 

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Re: 100 MHZ counter design in SPARTAN 3

Thanks Bob,

 

If you agree that FPGA counters do work as intended, and you are seeing counter mismatches between FPGAs, there should be a logical explanation for the mismatches.

 

Yes thats what I need to find out. Let say the accumulated drift over duration  ( 60  minutes in this case ) is from the clocking source (oscillator), then this drift should be seen in all the plots. Am I correct ? 

 

Thanks mcgett,

 

Your assumption that the relative error between the two clocks is zero because the devices have the same specifications is wrong. These devices have a lower PPM variance, but it isn't zero

 

Yes I follow.  It won't be zero, but it may be negiligble

 

Thanks Dr John smith,

 

Can I suggest that you just put one scope probe on each of the two clocks on the boards,
   and look how the clocks seem on the display.
   you will see that the two clocks are
     a) different frequencies
     b) arbitery phase
     c) different jitters.

 

Different frequencies ?? . Both frequencies   will not be same. But the difference between two clock  frequencies  should be negiligble. If it is  not , second trace will not be seen in  the oscilloscope.


Also DCM  will reduce the phase noise .   Please correct me 

 

Kind Regards


Faisal

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Registered: ‎07-21-2009

Re: 100 MHZ counter design in SPARTAN 3

Faisal, your timebase mis-match drift measurements seem to be completely bogus, if I read your report correctly.

 

  • Your 40-bit (or longer) counter requires considerably longer than 1 second to cycle from 0 to terminal count.
  • Your counter resets from the GPS pulse, once every second.
  • Your scope trigger logic produces only a single trigger event per 40-bit counter period
  • The offset between the two timebases should include the clock period of the timebase clock, which represents the clock phase uncertainty between the two timebases at the time of the reset input pulse.

For example: In the bit[8] measurement, you are capturing the 'drift' of (only) the first 2^8 counts since the last counter reset.  The counter reset re-aligns the counters (and timebases) being compared.  Therefore, the only "drift" being measured is the drift which occurs in the first 2^8 counts, and the rest of the "drift" is ignored.  Furthermore, the "measured" 1.6nS drift (it looks like 4nS drift, to me) is less than the expected 1 clock cycle (10nS @ 100MHz) uncertainty of the synchronised counter reset pulse.

 

In short

1. your measurement method is too limited, and does not reflect mismatch drift over a full 1 second period (between reset pulses)

 

2. your measurement traces don't include the unavoidable timing uncertainty between the two timebases of the reset pulse, suggesting the measurement method is fatally flawed and unusable.

 

Suggested change:

Trigger the 'scope directly from a counter bit output.  This will allow the scope display to show the accumulated mismatch drift over an entire 1 second period (the interval between reset pulses), rather than the drift over (only) a fraction of the 1-second period.

 

With this change, there will be a fixed 1-clock period "mismatch drift" which reflects the reset pulse clock cycle uncertainty.  The fixed interval must be subtracted from the scope display waveform, for generating 'final' interpreted results.

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

hi

 

lets look at these two clocks first shall we. make certain they are doing what you think they are.

 

two probes on your scope ch 1 and ch 2.

  Put probe ch 1 on to board 1 clock, and probe ch 2 ontothe clock of the second board.

    what do you see ?

         if the clocks were identical , what shou;d you see ,?

             if one clock was say 1 Hz different in frequency than the other , what shpuld you see.

 

 

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Re: 100 MHZ counter design in SPARTAN 3

Many thanks  Bob .

Applogies for disurbing your patience.

Faisal, your timebase mis-match drift measurements seem to be completely bogus, if I read your report correctly.

Your 40-bit (or longer) counter requires considerably longer than 1 second to cycle from 0 to terminal count.
-

 

Yes I follow.

Your counter resets from the GPS pulse, once every second -

No, GPS pulse is used as trigger  which means to start the counter. After that GPS pulse is not used any more. Counter is free running  which means when counter reaches the limit it starts again

Your scope trigger logic produces only a single trigger event per 40-bit counter period ,

 

Yes.


Suggested change:

Trigger the 'scope directly from a counter bit output. Results posted are based on your suggestion which applies to 8 th and 16 th bit.


for 32 nd bit ,  I have two measurement cases


Measurement Case - (i)

in case of 32 nd  bit  , 32 nd  bit will high  for a duration of

( ( 2^32 -1) -2^31 ) * 10 nS  , which is nearly 21.47 seconds ,  Oscilloscope will see a 23.28 mHZ on the scope.

Please see the waveform on page 1 of the document attached  with scope resoultion of 10 seconds . This confirms that measurement setup is correctly monitoring the 32 nd bit.

Now please see the waveform on page 2 of the document attached  having scope reolution of 10 nano seconds.
Oscilloscope will see a trigger point for every 42.94 seconds.


Measurement Case - ( ii)

In this case  I have send a 1us  pulse whose  rising edge starts when  32 nd bit of the counter  toggles from zero to 1 . In this case  scope would see the rising edge for every 42.94 + 10 nS + 100 us .

Measurement point of view  , Case (i) and Case (ii) are same  . Am I right ?

 

Also for 38 th bit  , I have used measurement case  (ii) , Please see the waveform on page 3 of the document attached.

 

So far I have seen the accumulated drift over  60 minutes is around 4 nano seconds in all the cases (8 th , 16 th , 32 nd and 38 th bit)

 

Regards

 

Faisal

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Re: 100 MHZ counter design in SPARTAN 3

Your scope trigger logic produces only a single trigger event per 40-bit counter period ,

Yes.

You realise that this represents a low-pass filter on your drift measurements, agreed?

 

If you limit measurement to one trigger event per 40-bit counter period, and you are accumulating waveforms from one 40-bit cycle to the next, you should get the same measurement results for any of the counter bits.  In other words, there is no difference between using bit[8] and using bit[38].  The period/frequency of "samples" is the same.

 

If you want to include drift/jitter within a single 40-bit period in your measurements, you will need to remove the "one trigger per counter cycle" filter.  Selecting a high-order bit for comparison also infers a low-pass filter.  Selecting a low-order bit (bit[8], for example), infers much less of a low-pass filter.

Measurement point of view  , Case (i) and Case (ii) are same. Am I right ?

Agreed.

So far I have seen the accumulated drift over  60 minutes is around 4 nano seconds in all the cases (8th, 16th, 32nd and 38th bit)

Yes, because there is no useful difference between your measurements.  The intervals of the measurements are the same, because of the low-pass trigger filter.  Is this correct, or am I mistaken?

 

Please clarify for me --

Note this frequency is too low for drift measurement which is outside the capability of oscilloscope for this application. So procedure described before is slightly changed which is as follows

I don't understand how the period of the trigger pulse (bit[38] in this case) has any bearing on the measurement or the scope's ability to capture timebase drift.  If you are triggering the scope on a rising edge, why does the scope care how often that edge occurs?

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

Thanks again Bob,

 

You realise that this represents a low-pass filter on your drift measurements, agreed?

 

Yes the scope i/p from FPGA is of low frequency signal. Is that you mean ?

 

Selecting a high-order bit for comparison also infers a low-pass filter.  Selecting a low-order bit (bit[8], for example), infers much less of a low-pass filter.

 

Yes, I agree. Could you please add a bit more about what  you suggest ?

 

Yes, because there is no useful difference between your measurements.  The intervals of the measurements are the same, because of the low-pass trigger filter.  Is this correct, or am I mistaken?


The intervals of the measurements ( I mean triggering of scope are not same ) . I don't know whether I follow you correctly , From my little  knowledge inetrval of the measurements are  deterimed by bit position in the counter. For e.g  in case of 38 th bit trigger event occurs for every 22.9 minutes while  for every 42.49 seconds from the triggering point of FPGA.

 

Yes, because there is no useful difference between your measurements.  The intervals of the measurements are the same, because of the low-pass trigger filter.  Is this correct, or am I mistaken?

 

Could yo please explain a bit about the  real difference you  mean ?. I think  the final answer to this measurement lies in that difference.


 

I don't understand how the period of the trigger pulse (bit[38] in this case) has any bearing on the measurement or the scope's ability to capture timebase drift.  If you are triggering the scope on a rising edge, why does the scope care how often that edge occurs?

 

Let me re word . In order to confirm that scope is set to trigger on the 38 th bit , I need to display the frequency of the pulse similar to 32 nd bit. I don't think the oscilloscope  i have used can dispaly 363  micro Hz.

 

 

Regards

 

Faisal

 

 

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Re: 100 MHZ counter design in SPARTAN 3

Yes, because there is no useful difference between your measurements.  The intervals of the measurements are the same, because of the low-pass trigger filter.  Is this correct, or am I mistaken?

The intervals of the measurements ( I mean triggering of scope are not same ) . I don't know whether I follow you correctly, From my little knowledge inetrval of the measurements are deterimed by bit position in the counter. For e.g  in case of 38 th bit trigger event occurs for every 22.9 minutes while  for every 42.49 seconds from the triggering point of FPGA.

Because you trigger only once per counter cycle, the interval of your measurement (the time between scope triggers) is the cycle of the counter.  The only difference between triggering on the first edge of bit[8] instead of the first edge of bit[32] is the position of the trigger within the counter cycle interval.

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

Let me re word . In order to confirm that scope is set to trigger on the 38th bit , I need to display the frequency of the pulse similar to 32nd bit. I don't think the oscilloscope  i have used can dispaly 363  micro Hz.

Thank you for this explanation.  The drift measurements are not based on the pulse frequency or bit frequency, the pulse frequency waveform display is for information/verification purposes only.  Do I understand correctly?

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

If you want to include drift/jitter within a single 40-bit period in your measurements, you will need to remove the "one trigger per counter cycle" filter.  Selecting a high-order bit for comparison also infers a low-pass filter.  Selecting a low-order bit (bit[8], for example), infers much less of a low-pass filter.

 

Yes, I agree. Could you please add a bit more about what  you suggest ?

Instead of using your 'one trigger per counter cycle' logic -- which is a low-pass filter on your measurement samples -- you could use the counter bit selection as a low-pass filter.

 

Triggering on bit[40] should give you the same measurements you are obtaining with your existing trigger (low-pass) filter -- one sample per counter cycle.

 

Triggering on bit[39] should give you twice the drift sampling frequency you have now, halving the interval between samples.

 

Triggering on bit[8] should give you a drift sampling frequency of roughly 195KHz (100MHz divided by 512).

Triggering on bit[9] should give you a drift sampling frequency of roughly 98KHz (100MHz divided by 1024).

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

Bob,

 

Thanks

 

Thank you for this explanation.  The drift measurements are not based on the pulse frequency or bit frequency, the pulse frequency waveform display is for information/verification purposes only.  Do I understand correctly?


Pulse frequency waveform display is for information/verification purposes and the accumulated drift over 60 minutes .

 

 

Faisal

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Re: 100 MHZ counter design in SPARTAN 3

Pulse frequency waveform display is for information/verification purposes and the accumulated drift over 60 minutes.

Faisal,  I don't understand what this means.

 

Do you have a clear and concise description of what you are trying to measure, and (separately) how you are trying to perform the measurements?  I think these would be helpful.  If you've already posted these, please post them again.

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

Bob,

 

I wish  to make sure , whether I am in the right track or ?

 

Are you saying that measurement setp and measurement results posted does not reflect any of the drift  ( drift  sources  may Clocking source, FPGA and  auxillries ) accumulated over 60 minutes  ?

 

 

 

Triggering on bit[40] should give you the same measurements you are obtaining with your existing trigger (low-pass) filter -- one sample per counter cycle.

 

Triggering on bit[39] should give you twice the drift sampling frequency you have now, halving the interval between samples.

 

Triggering on bit[8] should give you a drift sampling frequency of roughly 195KHz (100MHz divided by 512).

Triggering on bit[9] should give you a drift sampling frequency of roughly 98KHz (100MHz divided by 1024).

 

Sorry , I can't follow you.


 

Kind Regards

 

Faisal

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Re: 100 MHZ counter design in SPARTAN 3

Faisal,

 

Are you triggering only once per counter cycle, or more than once per counter cycle?

 

If you are triggering only once per counter cycle:

  • the interval between triggers (or "samples") will be the same, no matter which counter bit you use to position the trigger
  • the sample frequency will be the same, no matter which counter bit you use to position the trigger

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

HI Faisal

 

to go back to your orrignal question,

 

   which was about counters drifting in the fpga,

 

do you think counter do drift in the FPGA ?

 

 

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Re: 100 MHZ counter design in SPARTAN 3

Thanks


Are you triggering only once per counter cycle, or more than once per counter cycle?

 

triggering you mean triggering the  FPGA board or triggering  the Oscilloscope ?

 

If your answer is  Oscilloscope

 

It is at normal mode  with  postiive rising edge trigger .

 

It will trigger when the required bit reaches the threshold setting . Next trigger is from the next count cycle. So for eg if  the monioring bit is 8 then the scope triggers when the counter reaches   binary 10000000.

 

 

If your answer is  FPGA


Both FPGA are triggered by a single 1 PPS pulse. Once FPGA got triggered  , counter is initiated and will be free running . . So 1 pps is used for the first time only. I expect  that if the  oscilltator dirft is high , then second trace will be moving from the trigger point (first trace) and one time it will disappear from the scope screen.


Faisal

 


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Re: 100 MHZ counter design in SPARTAN 3

Are you triggering the oscilloscope only once per counter cycle, or more than once per counter cycle?

You didn't answer the question, Faisal.  This is a critical point which must be established and understood.

Both FPGA are triggered by a single 1 PPS pulse.

You mean a single pulse.  The FPGAs are triggered once (and only once), and then free-run for the duration of your timebase drift measurements.

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

 

Bob ,Sorry

 

Are you triggering the oscilloscope only once per counter cycle, or more than once per counter cycle?

 

Once per counter cycle. Counter bit I used  to monitor is  only the MSB

 

Verilog code I used

 

For e.g  for the 8 th bit (MSB)

 

reg [7:0] counter;

 

For e.g  for the 16 th bit (MSB)

 

reg [15:0] counter;

 

For e.g  for the 24 th bit (MSB)

 

reg [23:0] counter;

 

 

You mean a single pulse.  The FPGAs are triggered once (and only once), and then free-run for the duration of your timebase drift measurements.

 

Yes it is.

 

Faisal

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Re: 100 MHZ counter design in SPARTAN 3

Once per counter cycle. Counter bit I used  to monitor is  only the MSB

If you are sampling once per counter cycle, it doesn't matter which counter bit you are using to generate the trigger.  The sampling frequency and the span over which you are sampling is the same.

 

  • You should not expect different results for using different counter bits, as sampling frequency and sampling duration are unchanged.
  • By reducing the sampling frequency (to 1 sample per counter cycle), you are applying a low-pass filter to your results.  The counter bit selected for trigger position does not matter.

Verilog code I used

For e.g  for the 8 th bit (MSB)

reg [7:0] counter;

For e.g  for the 16 th bit (MSB)

reg [15:0] counter;

For e.g  for the 24 th bit (MSB)

reg [23:0] counter;

I was under the impression you were not varying the width of the counter.  If you are varying the width of the counter, then the sample frequency would indeed change (with the change in counter cycle).  How were the drift measurements taken -- fixed counter cycle or varying counter cycle?

 

-- Bob Elkind

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Re: 100 MHZ counter design in SPARTAN 3

@drjohn,

do you think counter do drift in the FPGA ?

The thread title is misleading.  Faisal is measuring drift between two timebases.

 

-- Bob Elkind

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Re: 100 MHZ counter design in SPARTAN 3

Hi Bob,

 

you and I both know that two clocks on two different boards, are going to drift.

  but I'm not convinced Faisal is convinced of this yet.

 

I could be 120 % wrong, and if so I appologise, but there are comments even in late posts about the fpge drifting .

 

hence I'd like to know what Faisal sees when he probes the clocks on each board , one clock on each of the scope channels. 

 

Faisal  can you describe explain what you see on the scope ?

 

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Re: 100 MHZ counter design in SPARTAN 3

Thanks Dr John smith

 

you and I both know that two clocks on two different boards, are going to drift.

 

Yes it is the aim of the measurement. does the drift purely reley on clock source?


  but I'm not convinced Faisal is convinced of this yet.

 

I am not convinced . At this point of discussion , I wish to  attach  drift measurement which I have done early this year. That time oscillator used  was 100 MHz.. I am sure about the frequency of the oscillators (100 MHz). But No idea about frequency stability. Same design methodology was used to test the drift between two boards. Please see the attached.

 

hence I'd like to know what Faisal sees when he probes the clocks on each board , one clock on each of the scope channels. 

 

Faisal  can you describe explain what you see on the scope ?

 

Of course I can. Why you are very much particular in this test ?

 

Kind Regards

 

Faisal

 

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