cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Instructor
Instructor
2,891 Views
Registered: ‎07-21-2009

Measuring drift between two timebases

I usually try to lead Faisal along a path to understand certain principles of logic design and sampling theory and measurement techniques and...  [whatever the need of the moment might be].  After 20 or 30 posts, I usually give up on any pretenses of socratic method for professorial instruction, and I simply spell out what needs to be done -- leaving the explanations for later.  Faisal, I think, usually picks up on the concepts at hand (memo to myself, the less you write, the more Faisal learns).

 

This is to be expected.  I'm not sure if English is Faisal's native language (even if he is living in the UK), and I'm very sure that 'nerd English' is not Faisal's native language.  The subject matters of Faisal's threads do not lend themselves gracefully to forum post discussion.  Interactive discussion would be much more productive.

 

Having said all this, this thread has gone on long enough.  Here are my suggestions, and we'll let the underlying theory follow behind on its own schedule.

 

Faisal:

 

You are trying to measure the rate of drift between two timebases.  Here is how to do this.

 

  • Scope is in infinite persistence mode (you've learned this quite nicely, well done!).  Two probes, both channels (channels 0 and 1) displayed.  Trigger on rising edge, mid-level (between GND and signal HI)
  • Implement a free-running 8-bit binary counter in each FPGA (each timebase is 100MHz).

 

Rate of Drift from 0 to 10nS

  • Probe counter bit[0] of each FPGA (timebase).
  • Horizontal timebase is 2nS per div, 20nS across the 'scope display
  • Clear (reset) the scope persistence display.
  • Trace 0 will be a nice clean square wave with period = 20nS
  • Trace 1 will be a nice clean square wave at the start, smearing horizontally over time.
  • Measure the elapsed time it takes for Trace 1 rising edge to smear over to the (persistent display) falling edge, or the falling edge to smear over to the rising edge.
  • Measured drift rate is [10nS divided by elapsed time].

 

Rate of Drift from 0 to 20nS

  • Probe counter bit[1] of each FPGA (timebase).
  • Horizontal timebase is 5nS per div, 50nS across the 'scope display
  • Clear (reset) the scope persistence display.
  • Trace 0 will be a nice clean square wave with period = 40nS
  • Trace 1 will be a nice clean square wave at the start, smearing horizontally over time.
  • Measure the elapsed time it takes for Trace 1 rising edge to smear over to the (persistent display) falling edge, or the falling edge to smear over to the rising edge.
  • Measured drift rate is [20nS divided by elapsed time].

 

Rate of Drift from 0 to 40nS

  • Probe counter bit[2] of each FPGA (timebase).
  • Horizontal timebase is 10nS per div, 100nS across the 'scope display
  • Clear (reset) the scope persistence display.
  • Trace 0 will be a nice clean square wave with period = 80nS
  • Trace 1 will be a nice clean square wave at the start, smearing horizontally over time.
  • Measure the elapsed time it takes for Trace 1 rising edge to smear over to the (persistent display) falling edge, or the falling edge to smear over to the rising edge.
  • Measured drift rate is [40nS divided by elapsed time].

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Teacher
Teacher
2,866 Views
Registered: ‎07-09-2009

Re: 100 MHZ counter design in SPARTAN 3

Morning Faisal

 

you ask why am I particular,

 

its because the fundamentals are essential, and you have implied on a number of occassions that you have tow board with exactly 100 MHz on them, apart from drift.

 

where as this is not true,

 

you have two boards with 100 Mhz on them +- 0.5 ppm.

    hence they are VERY unlikely to have the same frequency.

 

even if you have two rubian clocks , they do NOT produce the same frequency,

   the atomic clocks around the world are averaged to achiev UTC.

 

if you put scope porbes on the ref clock output of two atomic clocks, you do get a beet frequency which is the differsance in frequency between them. OK it s small , VERY small, but it is there.

 

this is what I am hoping you can expalin,

 

but I'll leave you to the forum now,

   have a good synth.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Explorer
Explorer
2,859 Views
Registered: ‎07-28-2010

Re: Measuring drift between two timebases

Bob

 

Many Thanks and Sorry for disturbing your patience.

 

I'm not sure if English is Faisal's native language (even if he is living in the UK), and I'm very sure that 'nerd English' is not Faisal's native language.

 

Yes , I am not a native speaker of english and I heared language is not a barrier. In my case it does not work .

 

Time response of my brain is too slow to catch up. Also I haven't studied any digital design as part of my course rather than basic digital electronics. This is one of the reason  why I have encounterd all difficulties in the journey of embedded design.

 

Cultural and traditional  difference  also matters in dealing with nerd's like you,supervisor e.t.c. I should change.

 

Many thanks for your support right from the begining.

 

Kind Regards

 

Faisal

 

 

0 Kudos