06-15-2010 12:26 AM - edited 06-15-2010 12:34 AM
I would like to connect 6 ADCs, each with 8ch @ 12b / 30MHz, almost the same as in xapp774 (LVDS inputs with adcclk, lclk and data), but using Spartan 6 way.
As my application may be quite concerned with power and ressources saving, I'd prefer not using DCM or PLL, and anyway I guess I won't have the choice as there won't be enough of them for all those ADCs + other interfaces.
I have been using almost the same ADCs in previous projects but using only 4 ADCs, @ 50MHz and on Spartan-3A DSP and then Virtex-5 SX.
With Spartan-3A, I used 1 DCM and 2 region clocks (lclk and lclk180) for each ADC, and deserialization was done using FPGA standard logic. However I had to optimize carefully my circuit to be able to achieve 300MHz. adcclk signal was not used as a clock but as a framing signal.
With Virtex-5, I've been able to use IODELAY+ISERDES, delivering 6b for each ISERDES on the LVDS pair (even/odd bits), without using DCM or PLL and using adcclk as divclk through BUFR. lclk and lclk180 were used through BUFIOs.
As regards the calibration process, we prefer using fixed data patterns produced by ADC. We then make DCM phase (S3A) or IODELAYs (V5) vary to check the window where valid data can be acquired, and then take the center of it.
This time I think I will use a rather small Spartan-6 LX45 (which seems to be one of the only S6 easily available this summer). I would have prefered to do something like I did with V5 but this is not directly possible with S6 as its ISERDES only has a 4b parallel output. I was considering using a method shown in xapp1064 but I am now considering this is not applicable for my case (using too many PLLs).
I am then thinking about using the same method as the one I used with S3A, but replacing the DCMs phase shift by IODELAY's, as the frequency is rather low this time.
-- Questions --
Do you think there is a smarter method ?
Is Spartan-6 ISERDES out of purpose concerning ADCs over 10b ?
Will Xilinx release an application note for ADC interfaces on Spartan-6 ?
06-15-2010 08:34 AM - edited 06-15-2010 08:38 AM
At those frequencies I think you might still be able to get it done in the fabric especially if they use DDR. What is the exact ADC you are planning to use? It might also be possible to use the ISERDES to go to the 6 bits parallel and then widen it to 12 in the fabric.
06-15-2010 08:27 PM
I forgot to precise this point but yest, the interface is DDR.
The ADC is not completely decided. One of them is not yet released. Another is the AD9273. They have the same LVDS interface as the ADS527x.
The ADC sampling rate is finally more likely to be 40M, it could even be 50M but I guess we'll stay at 40.
06-15-2010 08:32 PM
> It might also be possible to use the ISERDES to go to the 6 bits parallel and then widen it to 12 in the fabric.
I guessed in this case I would need some PLL or DCM to get a double frequency frame clock from the frame clock provided by the ADC. And as I have 6 ADC, this requires too many.
Recently I am thinking the solution in this case would be to use only one of the 6 frame clocks provided by the 6 ADCs, as the clock source is the same for all of them. However, I expect some skew, though I should be able to compensate it with all the IODELAYs on bit clock and data IOs.
Also I am a bit confused about what strobe signal I should provide to the ISERDES in my case.
06-16-2010 11:32 AM - edited 06-16-2010 03:32 PM
> I guessed in this case I would need some PLL or DCM to get a double frequency frame clock from the frame clock provided by the ADC. And as I have 6 ADC, this requires too many.
If you were working with a full speed LVDS clock would not need to use a PLL to do a 1 to 6 DDR interface. (See serdes_1_to_n_clk_ddr_s8_diff.v in XAPP1064.) After looking at the timing diagrams for the AD9273, I would a agree that at least one PLL is needed and it would then be a matter of controlling the skew.
06-16-2010 09:23 PM
Thank you for your support. I am going to decide what method to use soon.
However, do you have some information about my other questions :
1) Is Spartan-6 ISERDES out of purpose concerning ADCs over 8b (in the same way, Virtex-5 ISERDES seems to be out of purpose for ADCs over 10b) ?
2) Will Xilinx release an application note for ADC interfaces on Spartan-6 (as with Spartan3A xapp774 and Virtex-5 xapp0866) ?
Thank you very much.
06-17-2010 02:52 PM
> 1) Is Spartan-6 ISERDES out of purpose concerning ADCs over 8b (in the same way, Virtex-5 ISERDES seems to be out of purpose for ADCs over 10b) ?
I would say yes, but the Spartan-6 should be able to manage to get job done much the same way that Virtex-5 does 12 bit (and higher) ADC's in XAPP866.
>2) Will Xilinx release an application note for ADC interfaces on Spartan-6 (as with Spartan3A xapp774 and Virtex-5 xapp0866) ?
There is a plan to do one. I am trying to get you a ballpark date on the schedule. It doesn't sound like it is imminent.
03-23-2012 09:43 PM
Can you give me the XAPP866.zip in the PDF xapp866.pdf?
The reference design files are available for download from:
This ZIP file contains:
• Ads527x_V4_V5: Classical implementation of a one-wire interface. Originally developed
for ADS527x ADC devices. [Ref 1]
• Ads6000_V4_1w_NoBramNoProc: A one-wire implementation of an ADS6xxx interface
for a Virtex-4 device.
• Ads6000_V4_2w_NoBramNoProc: A two-wire implementation of an ADS6xxx interface for
a Virtex-4 device.
• Ads_Usb_To_Uart: A sample design to connect the ADC SPI port via a UART_2_USB
device to a PC. This design uses a PicoBlaze processor core.
Both one-wire and two-wire implementations are identical. The two-wire design is preset for
two-wire applications, and the one-wire design is preset for one-wire applications.
But I find the link is not right ?
Please give me the XAPP866.zip which is described in the mail. Thank you very much.