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Contributor
Contributor
6,867 Views
Registered: ‎02-04-2008

16x8 ROM implementation on Spartan3A

Hi guys!

 

In brief: I am having trouble while compiling a 16x8 ROM. The ISE 11.1 goes mad and throws the following errors that I am not able to find any answers to:

 


ERROR:PhysDesignRules:1149 - Dangling pins on block:<ROM16x8/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3a_init. ram/spram.ram>:<RAMB16BWE_RAMB16BWE>.  Dangling input address pin for RAMB16BWE_RAMB16BWE. Address pins ADDRA13 thru ADDRA5 must be connected.

ERROR:PhysDesignRules:1170 - Dangling pins on block:<ROM16x8/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3a_init. ram/spram.ram>:<RAMB16BWE_RAMB16BWE>.  Dangling input address pin for RAMB16BWE_RAMB16BWE. Address pins ADDRB13 thru ADDRB5 must be connected.

ERROR:Bitgen:25 - DRC detected 2 errors and 5 warnings.  Please see the previously displayed individual error or warning messages for more details.


 

Please, help me to figure out the problem

 

In more details: I am trying to implement a simple ROM that has 16 rows of 8-bit values. For test purposes I try to compile it for the AVNET Spartan 3A Evaluation Kit with Spartan3A 400K gates on it. I am using the ISE 11.1 and the CoreGenerator to produce the ROM memory. Here are all the files of my project - the purpose here is to cycle relatively slowly through the memory contents and to output the 4 LSB on 4 LEDs that are available on-board.

 

The "memory" module (top module) - 'rom16' is the core, filled with the values from a COE file:


module memory(

input clk,

input rst,

input enable,

output [3:0] leds

    );

 

reg [3:0] addra = 0;

wire [7:0] douta;

   reg [13:0] count = 0;//2^14=16384

 

// clock divider

   always @(posedge clk or posedge rst)

if(rst)

count <= 0;

else

if (~enable)

count <= count + 1;

 

// single port 16x8 ROM

rom16 ROM16x8 (

.clka(clk),

.rsta(rst),

.addra(addra), // Bus [3 : 0] 

.douta(douta)); // Bus [7 : 0] 

 

   always @(count[13])

addra <= addra + 1;

assign leds = douta[3:0];

 

endmodule


 

 

 

The COE file:

MEMORY_INITIALIZATION_RADIX=2;
MEMORY_INITIALIZATION_VECTOR=
00000000,
00000001,
00000010,
00000011,
00000100,
00000101,
00000110,
00000111,
00001000,
00001001,
00001010,
00001011,
00001100,
00001101,
00001110,
00001111;

 
  
The UCF file:

NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 15.6 us HIGH 50 %;
NET "clk" LOC = T7;
NET "clk" IOSTANDARD = LVCMOS33;
NET "enable" LOC = K3;
NET "enable" IOSTANDARD = LVCMOS33;
NET "leds[0]" LOC = D14;
NET "leds[0]" IOSTANDARD = LVCMOS33;
NET "leds[1]" LOC = C16;
NET "leds[1]" IOSTANDARD = LVCMOS33;
NET "leds[2]" LOC = C15;
NET "leds[2]" IOSTANDARD = LVCMOS33;
NET "leds[3]" LOC = B15;
NET "leds[3]" IOSTANDARD = LVCMOS33;
NET "rst" LOC = H4;
NET "rst" IOSTANDARD = LVCMOS33;

 
 

 

Waiting to hear from you soon.

         Yassen

 

Message Edited by gorbounov on 01-18-2010 11:46 AM
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4 Replies
Historian
Historian
6,856 Views
Registered: ‎02-25-2008

Re: 16x8 ROM implementation on Spartan3A

As a first guess, your ROM address needs to be synchronous with the ROM's clock, not with some arbitrary bit generated by the counter.
----------------------------Yes, I do this for a living.
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Contributor
Contributor
6,854 Views
Registered: ‎02-04-2008

Re: 16x8 ROM implementation on Spartan3A

Thank's for your fast feedback.

In general you are right. But, now, when my code is changed as follows:


module memory(

input clk,

input rst,

input enable,

output [3:0] leds

    );

 

reg clka = 0;

reg [3:0] addra = 0;

wire [7:0] douta;

   reg [13:0] count = 0;//2^14=16384

 

// clock divider

   always @(posedge clk or posedge rst)

if(rst)

count <= 0;

else

if (~enable)

count <= count + 1;

 

// single port 16x8 ROM

rom16 ROM16x8 (

.clka(clka),

.rsta(rst),

.addra(addra), // Bus [3 : 0] 

.douta(douta)); // Bus [7 : 0] 

 

   always @(count[13])

clka = !clka;

always @(posedge clka)

addra <= addra + 1;

assign leds = douta[3:0];

endmodule


 

The situation is not any better. I got lost :( Maybe I have to continue the fight tomorrow...

The errors are here:


ERROR:Map:116 - The design is empty.  No processing will be done.

ERROR:Map:52 - Problem encountered processing RPMs. 

ERROR:Map:116 - The design is empty.  No processing will be done.

ERROR:Map:52 - Problem encountered processing RPMs. 

ERROR:PhysDesignRules:1146 - Dangling pins on block:<ROM16x8/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3a_init. ram/spram.ram>:<RAMB16BWE_RAMB16BWE>.  The control pins for the RAMB16BWE must be used.

ERROR:PhysDesignRules:1146 - Dangling pins on block:<ROM16x8/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3a_init. ram/spram.ram>:<RAMB16BWE_RAMB16BWE>.  The control pins for the RAMB16BWE must be used.

ERROR:Pack:1642 - Errors in physical DRC.


 

I am confused because of one more reason - this design (prev. post and the current one) performs well in simulation!!! It fails only when I try to synthesize. I doubt that the clock is the only reason. And those error messages with codes 1146 and 1170 can not be found in the Xilinx answers database. Please, give me some advice! I need it!

 

 Regards,

      Yassen

 

Message Edited by gorbounov on 01-18-2010 11:23 PM
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Contributor
Contributor
6,832 Views
Registered: ‎02-04-2008

Re: 16x8 ROM implementation on Spartan3A

One more thing. Does anybody knows whether I can use a tool like the "Data2MEM Memory Tool" to update the ROM contents in the '.bit' file directly without resynthesize the entire design. Can you provide some short example. Thanks!

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Highlighted
Newbie ivanrojas
Newbie
5,282 Views
Registered: ‎08-28-2013

Re: 16x8 ROM implementation on Spartan3A

Hey I'm having the exact same issue, did you get to solve it?

 


@gorbounov wrote:

Thank's for your fast feedback.

In general you are right. But, now, when my code is changed as follows:


module memory(

input clk,

input rst,

input enable,

output [3:0] leds

    );

 

reg clka = 0;

reg [3:0] addra = 0;

wire [7:0] douta;

   reg [13:0] count = 0;//2^14=16384

 

//clock divider

@   always @(posedge clk or posedge rst)

if(rst)

count <= 0;

else

if (~enable)

count <= count + 1;

 

//single port 16x8 ROM

rom16 ROM16x8 (

.clka(clka),

.rsta(rst),

.addra(addra), // Bus [3 : 0] 

.douta(douta)); // Bus [7 : 0] 

 

@   always @(count[13])

clka = !clka;

 

@always @(posedge clka)

addra <= addra + 1;

 

assign leds = douta[3:0];

endmodule


 

The situation is not any better. I got lost :( Maybe I have to continue the fight tomorrow...

The errors are here:


ERROR:Map:116 - The design is empty.  No processing will be done.

ERROR:Map:52 - Problem encountered processing RPMs. 

ERROR:Map:116 - The design is empty.  No processing will be done.

ERROR:Map:52 - Problem encountered processing RPMs. 

ERROR:PhysDesignRules:1146 - Dangling pins on block:<ROM16x8/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3a_init. ram/spram.ram>:<RAMB16BWE_RAMB16BWE>.  The control pins for the RAMB16BWE must be used.

ERROR:PhysDesignRules:1146 - Dangling pins on block:<ROM16x8/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3a_init. ram/spram.ram>:<RAMB16BWE_RAMB16BWE>.  The control pins for the RAMB16BWE must be used.

ERROR:Pack:1642 - Errors in physical DRC.


 

I am confused because of one more reason - this design (prev. post and the current one) performs well in simulation!!! It fails only when I try to synthesize. I doubt that the clock is the only reason. And those error messages with codes 1146 and 1170 can not be found in the Xilinx answers database. Please, give me some advice! I need it!

 

 Regards,

      Yassen

 

Message Edited by gorbounov on 01-18-2010 11:23 PM


@gorbounov wrote:

Thank's for your fast feedback.

In general you are right. But, now, when my code is changed as follows:


module memory(

input clk,

input rst,

input enable,

output [3:0] leds

    );

 

reg clka = 0;

reg [3:0] addra = 0;

wire [7:0] douta;

   reg [13:0] count = 0;//2^14=16384

 

//clock divider

@   always @(posedge clk or posedge rst)

if(rst)

count <= 0;

else

if (~enable)

count <= count + 1;

 

//single port 16x8 ROM

rom16 ROM16x8 (

.clka(clka),

.rsta(rst),

.addra(addra), // Bus [3 : 0] 

.douta(douta)); // Bus [7 : 0] 

 

@   always @(count[13])

clka = !clka;

 

@always @(posedge clka)

addra <= addra + 1;

 

assign leds = douta[3:0];

endmodule


 

The situation is not any better. I got lost :( Maybe I have to continue the fight tomorrow...

The errors are here:


ERROR:Map:116 - The design is empty.  No processing will be done.

ERROR:Map:52 - Problem encountered processing RPMs. 

ERROR:Map:116 - The design is empty.  No processing will be done.

ERROR:Map:52 - Problem encountered processing RPMs. 

ERROR:PhysDesignRules:1146 - Dangling pins on block:<ROM16x8/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3a_init. ram/spram.ram>:<RAMB16BWE_RAMB16BWE>.  The control pins for the RAMB16BWE must be used.

ERROR:PhysDesignRules:1146 - Dangling pins on block:<ROM16x8/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3a_init. ram/spram.ram>:<RAMB16BWE_RAMB16BWE>.  The control pins for the RAMB16BWE must be used.

ERROR:Pack:1642 - Errors in physical DRC.


 

I am confused because of one more reason - this design (prev. post and the current one) performs well in simulation!!! It fails only when I try to synthesize. I doubt that the clock is the only reason. And those error messages with codes 1146 and 1170 can not be found in the Xilinx answers database. Please, give me some advice! I need it!

 

 Regards,

      Yassen

 

Message Edited by gorbounov on 01-18-2010 11:23 PM



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