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Visitor
Visitor
4,242 Views
Registered: ‎02-10-2014

250 MHz system synchronous clock timing issues

Dear all,

 

I have an external device providing a 250 MHz clock to a Spartan 6 (SLX150T-2). I need to output a few signals registered to this clock with a 1.75 ns setup / 0 ns hold time. This means I have a clock-to-output time of max 2.25 ns, which I constrain with an OFFSET OUT. I use a DCM to phase shift the clock to meet the output setup time.

 

My problem is that the spread between 'max clk-to-pad' (2.222 ns) and 'min clk-to-pad' (-0.972 ns) is over 3 ns, making it impossible to meet my required timing.

For the slow path:

Clock delay: 1.572 ns

Data delay: 3.500 ns (majority Tioop, 1.982 ns, and Tockq, 1.080 ns)

 

For the fast path:

Clock delay: 1.074 ns

Data delay: 1.352 ns (majority Tioop, 0.699 ns, and Tockq, 0.336 ns)

 

So the delay change in the OLOGIC2 over PVT is what is killing me. Does anyone have any suggestions in how to get around this?

 

Best,

Chris

 

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Highlighted
Instructor
Instructor
4,240 Views
Registered: ‎07-21-2009

The DCM or PLL has a feedback input, yes?  Take the generated clock output, pass it through an input/output buffer (IOBUF) through an ODDR clock forwarding stage, and use the output clock (fed back as an input) for the DCM/PLL feedback.

 

The DCM/PLL will phase match (de-skew) the internal clock so that outputs (on the circuit board) are phase-matched to the 250MHz clock on the circuit board.

 

The path from input pin to DCM/PLL for both the source clock and the feedback clock must be matched, typically an IBUF + BUFIO2/BUFIO2FB pair.

 

Does this make sense?

 

The de-skewing should cancel the clock distribution delays (skews), the output register and buffer delays (skews), and the reference clock input delays (skews).

 

As an example, see UG382 Figure 3-13.

 

-- Bob Elkind

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Visitor
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Registered: ‎02-10-2014

This seems like an elegant solution, however however I have two questions:

 

1) This (seems to) require routing the clock out of the FPGA and then back into the pad that can drive the BUFIO2FB complementary to the GCLK input BUFIO. On my fabricated PCBs I do not have such a loop. I do have two spare (non-GCLK) pads connected together - is there any way of compensating the delay via these? Or perhaps rather than having one pad output the feedback clock to the feedback clock input, I can use an IOBUF and drive the feedback pad directly (not requiring anything on the PCB)?

 

 

2) Assuming I can solve (1), I have implemented the design in UG382 Figure 3-13 (Verilog outline below) to see how the timing report works out, but I cannot seem to see the deskewing in the timing report. I have constrained the input and feedback clocks to something sensible, and added a feedback constraint (NET "clkFB_i" FEEDBACK = 0.1 ns NET "clkFB_o").  The timing report however gives a slack of -6.5 ns on the 'offset out 2.25ns after clk_i' constraint. Am I missing something in my constraints, or am I misinterpreting the timing report?


BUFIO2 #(.DIVIDE_BYPASS("TRUE")) clkIn_BUFIO2_ins(
    .I(clk_i),
    .DIVCLK(pll_clkIn),
    .IOCLK(),
    .SERDESSTROBE()
);

IBUF clkFB_IBUF(
    .I(clkFB_i),
    .O(clkFB_bufiofb)
);

BUFIO2FB #(.DIVIDE_BYPASS("TRUE")) clkFB_BUFIO2FB_ins(
    .I(clkFB_bufiofb),
    .O(pll_clkFB_in)
);

PLL_BASE #(
    .COMPENSATION("EXTERNAL"),
    .CLK_FEEDBACK("CLKFBOUT"),
    .CLKIN_PERIOD(4.0),
    .CLKFBOUT_MULT(2),
    .CLKOUT0_DIVIDE(2),
    .DIVCLK_DIVIDE(1)
    ) pll_ins(
    .CLKIN(pll_clkIn),
    .CLKFBIN(pll_clkFB_in),
    .CLKOUT0(clk),
    .CLKFBOUT(pll_clkFB_out)
);

BUFG clkFB_BUFG_ins(
    .I(pll_clkFB_out),
    .O(clkFB_bufg)
);

ODDR2 clkFB_ODDR2_ins(
    .D0(1'h1),
    .D1(1'h0),
    .C0(clkFB_bufg),
    .C1(~clkFB_bufg),
    .Q(clkFB_o),
    .CE(1'h1)
);

 

 

Paths for end point dataOut_o (F15.PAD), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  -6.544ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               dataOut (FF)
  Destination:          dataOut_o (PAD)
  Source Clock:         clk rising at 0.000ns
  Requirement:          2.250ns
  Data Path Delay:      3.500ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
  Clock Path Delay:     5.015ns (Levels of Logic = 3)
  Clock Uncertainty:    0.279ns

  Clock Uncertainty:          0.279ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Discrete Jitter (DJ):       0.126ns
    Phase Error (PE):           0.211ns

  Maximum Clock Path at Slow Process Corner: clk_i to dataOut
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B15.I                Tiopi                 1.557   clk_i
                                                       clk_i
                                                       clkIn_IBUFG_ins
                                                       ProtoComp1.IMUX.1
    BUFIO2_X2Y26.I       net (fanout=1)        0.626   clkBufG
    BUFIO2_X2Y26.DIVCLK  Tbufcko_DIVCLK        0.190   clkIn_BUFIO2_ins
                                                       clkIn_BUFIO2_ins
    PLL_ADV_X0Y5.CLKIN1  net (fanout=1)        0.885   pll_clkIn
    PLL_ADV_X0Y5.CLKOUT0 Tpllcko_CLK           0.000   pll_ins/PLL_ADV
                                                       pll_ins/PLL_ADV
    OLOGIC_X17Y173.CLK0  net (fanout=2)        1.757   clk
    -------------------------------------------------  ---------------------------
    Total                                      5.015ns (1.747ns logic, 3.268ns route)
                                                       (34.8% logic, 65.2% route)

  Maximum Data Path at Slow Process Corner: dataOut to dataOut_o
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X17Y173.OQ    Tockq                 1.080   dataOut
                                                       dataOut
    F15.O                net (fanout=1)        0.438   dataOut
    F15.PAD              Tioop                 1.982   dataOut_o
                                                       dataOut_o_OBUF
                                                       dataOut_o
    -------------------------------------------------  ---------------------------
    Total                                      3.500ns (3.062ns logic, 0.438ns route)
                                                       (87.5% logic, 12.5% route)

 

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Highlighted
Instructor
Instructor
4,202 Views
Registered: ‎07-21-2009

1) ... Or perhaps rather than having one pad output the feedback clock to the feedback clock input, I can use an IOBUF and drive the feedback pad directly (not requiring anything on the PCB)?

 

This should work.  Matching is best if both the reference clock and the feedback clock are on GCLK pins.

 

As for the timing constraints...  I would not worry about them in this particular application.  If you think about the implementation long enough, there are two fundamental skew components between the input reference clock and your registered outputs.  Neither of these skew components can be eliminated or reduced, they are fundamental in the Spartan-6 device family:

 

1.  The PLL phase matching between reference and feedback

 

2.  The within-device clock-to-output register delay matching of the output signals to the feedback clock.

 

I do not see a dependable alternative implementation which would avoid or reduce either of these two skew components -- and I am not sure that your application requirements need tighter skews than that which these two components represent.

 

As for your code, the following changes should be made:

 

1.  the ODDR2 output should connect to an IOBUF.

2.  the output of the IOBUF's input buffer should drive a BUFIO2FB, which in turn drives the PLL CLKFB input.  The BUFIO2FB output is what is phase-aligned with the input reference clock (which also passes through a BUFIO2).

3.  Instead of generating a separate clock output on the CLKFBOUT pin of the PLL, use the CLKOUT0 output clock only. 

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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