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Adventurer
Adventurer
8,883 Views
Registered: ‎03-01-2010

A 208-pin QFP Spartan 6. A possibility?

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A 208-pin QFP Spartan 6 package should be available IMO. But just my opinion...

 

Let's make it "Our" opinion! Vote by posting here in agreeance... Or disagreement...

 

Hmm, hopefully admin will tolerate this experiment.

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Teacher eteam00
Teacher
10,620 Views
Registered: ‎07-21-2009

Spartan-6 for hobby/prototyping

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I foresee problems with a 324-pin BGA using only 2 signal layers just by the inherent nature of the BGA layout, even 1mm spacing.

 

Be creative.  Don't try to get access to every user IO pin on every row.

 

The two outermost rows should be accessible using only the top layer.  The next two rows should be accessible using only the bottom layer.

 

If you use the FT256 or FG484 package with 1mm pitch, and you can manage 2 traces between pads, then you should be able to access 3 outermost rows on top layer and next 3 rows on the bottom layer.

 

If you want to use MCB, you will need a minimum of 4 signal layers (plus 2 plane layers) to access all the DRAM interface pins.

 

-- Bob Elkind

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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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Teacher eteam00
Teacher
8,870 Views
Registered: ‎07-21-2009

Re: A 208-pin QFP Spartan 6. A possibility?

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A 208-pin QFP Spartan 6 package should be available IMO.

 

Austin Lesea is the right person to authoritatively answer this question, but I will not let my limited insight deter me from offering my own answers.  Hold onto your knickers!

 

No.  NO.  No.  period and full stop, plain and simple.

 

Here's why.

 

  • Package lead inductance compromises IO bandwidth and signal slew rates.  Forget about DDR3-800.
  • Limited IO count.  After JTAG and supply/GND pins are subtracted, available user IO count limits suitable applications.
  • Thermal properties.  PQ208 plastic package is thermally inefficient, limiting device utilisation and bandwidth.  Theta J-C is much better with a copper-tungsten thermal slug in the package, but that's an expensive and unpopular solution.
  • Board area. 940 square mm (30.6mm on a side) footprint, more than 3x the area of the FT256 package.  The only good thing you can say about the size of the PQ208 is that it is still smaller than a PQ240 package.  By comparison the FT256 package is 289 square mm (17mm on a side).
  • Assembly/storage/handling yield.  208 pins which are very flexible.  If one of the leads is not co-planar with the other 207 leads (and straight!), the board needs to be tossed on the stack to be debugged and reworked.
  • Reliability.  The plastic seals around the leads are not sturdy, and moisture contamination is more of a problem than with a BGA.

If you can settle for the performance, IO count, and thermal limitations of the PQ208, your application is likely suitable for a Spartan-3e (rather than Spartan-6) solution.

 

The only redeeming attributes of QFPs are:

  • Leads can be visually inspected.
  • Leads can be lifted and jumpered.
  • With enough skill and patience, some people can convince themselves that PQFPs can be hand-soldered (unlike BGAs).  Unfortunately, almost any DRAM or processor on the same board will make hand assembly impractical.

In bygone days of SOICs and PLCCs, QFPs were easier to view with affection.  With the prevalence of BGA packages for just about everything (and not just FPGAs), it's time to leave the old "aircraft-carrier" packages behind.

 

-- Bob Elkind

SIGNATURE:
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Summary:
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Teacher eteam00
Teacher
8,862 Views
Registered: ‎07-21-2009

Your turn?

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A 208-pin QFP Spartan 6 package should be available IMO. But just my opinion.

 

What seems to be missing is the reasons upon which your opinion is based.  By all means, you should elaborate on why an army of customers should clamor for the QFP208, and why Xilinx will make even greater profits by responding favourably to this groundswell of demand.

 

There is no wrong or right answer.  Selecting which packages to offer involves tradeoffs.  Now that you raise the subject (a good discussion topic), don't be shy about expressing your opinions beyond the simple 'I like it'.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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Adventurer
Adventurer
8,855 Views
Registered: ‎03-01-2010

Re: A 208-pin QFP Spartan 6. A possibility?

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1) "Package lead inductance compromises IO bandwidth and signal slew rates".

Inductance and slew rates can be controlled, by a certain degree, by DRIVE and SLEW settings in a .UCF file to accomodate many designs. This is primarily up to the board designer, hence they would be to blame.

2) "...Limited IO count...".

Limited I/O count is why I am humbly proposing a higher pin QFP... BTW, 240-pin would be nice too... If 1 pin is off it is usually a techinicians' fault. Surely not Xilinx' fault, or even a distributers' fault. I know Avnet will ship 1 QFP in a tray meant for a full 20+ or more IC's for safe, static-free transport.

3) "If you can settle for the performance, IO count, and thermal limitations of the PQ208, your application is likely suitable for a Spartan-3e (rather than Spartan-6) solution."

The S6 has MCB's and PLL's and 6-input LUT's and is likely to be supported in the future beyond S3E...

 

4) "With enough skill and patience, some people can convince themselves that PQFPs can be hand-soldered (unlike BGAs). "

We are these people. We do not purchase the hundreds of thousands of units per user, but hundreds of thousands of users purchase many device(s) per order. We need to be able to prototype with the larger devices without committing to BGA, since this would require the involvement of undesired entities.

 

Bob, thanks for our input(s). So your vote is a -1 for proposed 208+pin QFP?

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Adventurer
Adventurer
8,842 Views
Registered: ‎03-01-2010

Re: A 208-pin QFP Spartan 6. A possibility?

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By the way, it would be a mistake for anyone to assume that I still wirewrap my current designs, based on my nick...
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Instructor
Instructor
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Registered: ‎08-14-2007

Re: A 208-pin QFP Spartan 6. A possibility?

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Low-quantity low-end parts are not really in Xilinx's niche.  If you look at Lattice, who seems eager

to pick up these customers, you'll find ECP2 (but not ECP3 or newer) parts in PQFP packaging.

I want to echo the sentiment that these packages are not suitable for high-speed I/O design.

Even the smaller (and lower inductance) TQ144 package in the Lattice ECP2 turned out to

have too much ground bounce to be useful in a Camera Link application (although their

256-ball FPGA worked a charm).

 

If you don't want to assemble BGA's onto boards, send them out to a contract manufacturer.

There are lots of them around, hungry for even low volume jobs.  Many will even place your

BGA's and let you finish the boards by hand.

 

You can also buy modules with a Spartan 6 and RAM on them, ready to hand solder onto

a base board if you're doing some really low-volume or hobby projects.

 

You'll also find CPLD's in TQFP's but remember that these don't have the density or

other features you've come to expect from FPGA's.  But Spartan-6 in a large quad flat

pack is a non-starter.

 

-- Gabor

-- Gabor
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Teacher eteam00
Teacher
8,835 Views
Registered: ‎07-21-2009

Re: A 208-pin QFP Spartan 6. A possibility?

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Inductance and slew rates can be controlled, by a certain degree, by DRIVE and SLEW settings in a .UCF file to accomodate many designs. This is primarily up to the board designer, hence they would be to blame.

 

Yes, when driving from the FPGA to the board.  The ugly parasitics of the package limit the usable IO bandwidth -- the question is 'how much'.  I'm not expert enough to assert that a separate set of datasheet specifications would be required for application to a Spartan-6 device in a PQ208 package, but this seems plausible.

 

If 1 pin is off it is usually a techinicians' fault. Surely not Xilinx' fault, or even a distributers' fault.

 

Blame is not as much the issue as cost of prevention and/or repair.  All the leads are exposed and vulnerable to displacement in two axes.

 

The S6 has MCB's and PLL's and 6-input LUT's and is likely to be supported in the future beyond S3E.

 

The 6-input LUTs translate to performance, right?.  You can always toss enough 5-input LUTs at the problem to match the equivalent logic of the 6-input LUTs, if you don't mind the occasional extra levels of delay.

 

MCBs are likely a non factor, as the PQ208 available pincount limits MCB usage to x8 devices, and lower operating frequencies.  What good is a MCB in a PQ208 if you cannot (fully) use it?  You may be better off with a soft MIG-generated controller targeted to a Spartan-3e device (just a wild untested guess).

 

The additional clock generation resources in S6 (vs. S3e) are a definite plus.  Is it enough of an enticement to slide your design into this shiny sleek S6 in a BGA324 package?

 

We need to be able to prototype with the larger devices without committing to BGA, since this would require the involvement of undesired entities.

 

Should we infer that "undesired entities" translates to competent board assembly houses with pick-and-place machines (which need to be programmed) and IR reflow process lines, which charge 1000s of dollars for setup and teardown (and programming, and solder stencils) for assembling even a single board?

 

Here is an alternate solution:

 

  • Find an assembly house which is fully competent to assemble mainstream surface mount boards (including .8mm BGAs).  The assembly house will have a rework station for removing and replacing BGAs.
  • Assemble by hand all the components you can manage on your own.
  • Bring the partially assembled boards and the remaining components to the assembly house, and ask them to mount the remaining packages -- using their rework station.  They will likely charge by the hour, and the out-of-pocket expenses are likely much lower than handing them the entire kit for assembly.
  • Rework stations have certain minimum board layout requirements (e.g. spacing restriction, restrictions on components mounted on the opposite side of the board, etrc.).  Have the board assembly house review your board layout for manufacturability (DFM) before you order the fabricated boards.

Does this make sense?

 

-- Bob Elkind

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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Adventurer
Adventurer
8,830 Views
Registered: ‎03-01-2010

Re: A 208-pin QFP Spartan 6. A possibility?

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Gabor, You're talking about a highest speed serial application... Your suggestion of CPLD's will not do when BRAMs are needed for softcore CPUs. Also, any S6 should be considered a higherend product niche... How about a lower speed grade "aircraft carrier", as Bob calls it. Some of us need slower, but more parallel  I/O. Maybe have a -3 speed grade 144-pin QFP, and a -2 speed grade 208/240-pin QFP?

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Teacher eteam00
Teacher
8,827 Views
Registered: ‎07-21-2009

Re: A 208-pin QFP Spartan 6. A possibility?

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Your suggestion of CPLD's will not do when BRAMs are needed for softcore CPUs.

 

Hmmm...   Have you met our wire-wrapping, CPLD-hugging friend Roger ?  :=)

 

How about a lower speed grade "aircraft carrier", as Bob calls it. Some of us need slower, but more parallel  I/O. Maybe have a -3 speed grade 144-pin QFP, and a -2 speed grade 208/240-pin QFP?

 

The engineering expense of a complete performance characterisation project is considerable (note: this is a dramatic understatement).  How many millions of these Spartan-6 devices in PQ208 packages do you think Xilinx will sell to offset this expense?  By definition, the answer is 'not enough'.  The PQ208 package is not cost-effective for volume applications, so its market is limited to small-volume projects.

 

Bottom line:  This is not going to happen.  Xilinx is putting all their engineering efforts into Gen 7 and beyond, Spartan-6 is strictly in maintenance engineering phase.  If you want to make a pitch to Xilinx, your target should be the next device family generation beyond 7.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Adventurer
Adventurer
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Registered: ‎03-01-2010

Re: A 208-pin QFP Spartan 6. A possibility?

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Bob, it does make sense... However, here's my perspective from a hobbyist point of view: I can buy 3 small 4-layer boards for $100US and design a 144-pin QFP S6 into it no problem. VCCO/VCCAUX/VCCINT included. Granted, 208+pins would be more challenging, but I foresee problems with a 324-pin BGA using only 2 signal layers just by the inherent nature of the BGA layout, even 1mm spacing.
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Adventurer
Adventurer
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Registered: ‎03-01-2010

Re: A 208-pin QFP Spartan 6. A possibility?

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Ok, well I tried... Can't fault me for that. Thanks for your eyes and ears.

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Instructor
Instructor
7,924 Views
Registered: ‎08-14-2007

Re: A 208-pin QFP Spartan 6. A possibility?

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@wirewrapper wrote:
Bob, it does make sense... However, here's my perspective from a hobbyist point of view: I can buy 3 small 4-layer boards for $100US and design a 144-pin QFP S6 into it no problem. VCCO/VCCAUX/VCCINT included. Granted, 208+pins would be more challenging, but I foresee problems with a 324-pin BGA using only 2 signal layers just by the inherent nature of the BGA layout, even 1mm spacing.

So place 2, 3, or 4 of those 144-pin TQFP's on your board to get the pins count up.  Just add

enough interconnect between chips to get the job done.  I've done lots of designs where I

couldn't get everything I wanted in one chip - at least at a reasonable price.  Using multiple

packages is often the cheapest way to get a higher pin count without breaking the bank.

 

-- Gabor

-- Gabor
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Teacher eteam00
Teacher
10,621 Views
Registered: ‎07-21-2009

Spartan-6 for hobby/prototyping

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I foresee problems with a 324-pin BGA using only 2 signal layers just by the inherent nature of the BGA layout, even 1mm spacing.

 

Be creative.  Don't try to get access to every user IO pin on every row.

 

The two outermost rows should be accessible using only the top layer.  The next two rows should be accessible using only the bottom layer.

 

If you use the FT256 or FG484 package with 1mm pitch, and you can manage 2 traces between pads, then you should be able to access 3 outermost rows on top layer and next 3 rows on the bottom layer.

 

If you want to use MCB, you will need a minimum of 4 signal layers (plus 2 plane layers) to access all the DRAM interface pins.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Adventurer
Adventurer
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Registered: ‎03-01-2010

Re: Spartan-6 for hobby/prototyping

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Thanks Gabor and Bob for responding to this post. You guys are Aces. I had to give the solution to Bob, because he suggested something that fit with my current board limitations. Albeit, an unattainable BGA process... Gabor, you mentioned earlier of assembly houses that place and weld BGA parts, what companies would you recommend?
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Historian
Historian
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Registered: ‎02-25-2008

Re: Spartan-6 for hobby/prototyping

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@wirewrapper wrote:
Thanks Gabor and Bob for responding to this post. You guys are Aces. I had to give the solution to Bob, because he suggested something that fit with my current board limitations. Albeit, an unattainable BGA process... Gabor, you mentioned earlier of assembly houses that place and weld BGA parts, what companies would you recommend?

Where are you located? It might be easier to recommend a house that's local to you.

----------------------------Yes, I do this for a living.
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Participant sjg69
Participant
7,791 Views
Registered: ‎03-29-2012

Re: Spartan-6 for hobby/prototyping

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@eteam00 wrote:

I foresee problems with a 324-pin BGA using only 2 signal layers just by the inherent nature of the BGA layout, even 1mm spacing.

 

Be creative.  Don't try to get access to every user IO pin on every row.

 

The two outermost rows should be accessible using only the top layer.  The next two rows should be accessible using only the bottom layer.

 

If you use the FT256 or FG484 package with 1mm pitch, and you can manage 2 traces between pads, then you should be able to access 3 outermost rows on top layer and next 3 rows on the bottom layer.

 

??

 

How does that work ? As soon s you lay down a row of vias for the third or fourth row of balls, you're limited to he space between vias for all successively inner rows, which as far as I can tell means 1 (maybe 2 with 4-mil trace/space in 1mm BGA)  trace between each via. So every successive row needs a new layer, AFAICT.

 

Thinking about getting one of Zephyrtronics BGA stations to help out with BGA at home, it quickly pays for itself when BGA pavement is $100 to $150... I've given up on getting QFP style packages for any reasonable pinout quantity from Xilinx...

 

Simon

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Teacher eteam00
Teacher
7,786 Views
Registered: ‎07-21-2009

Re: Spartan-6 for hobby/prototyping

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Thinking about getting one of Zephyrtronics BGA stations to help out with BGA at home

 

Does the BGA station come with operator training and board profiling instructions?

Does it come with an X-ray machine for checking BGA ball attach?

 

By all means post your experiences with this BGA station when you think you have learned to operate it.  This will be very interesting to folks who are not interested in hiring out experienced and capable services for this aspect of their designs.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant sjg69
Participant
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Registered: ‎03-29-2012

Re: Spartan-6 for hobby/prototyping

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Saw you'd replied, and was rather hoping to read about how to get 6-deep balls traced out to the BGA's periphery on 2 layers past the row of vias...

 

I've done BGA at home with some reasonable (~75%) success already using a simple IR oven. There's nothing too scary about getting them to attach, the problem (for me at least) is with alignment, which is where the ZT7 comes in. I'm not suggesting it's a tool for mass production, but with more and more of the chips I'm interested in coming as BGA only, it'd be nice to not pay the extra for mounting parts, and not to have an extra 2 weeks delay either.

 

Of course it follows the standard board heating profile(s); there's no x-ray, but I did think it might be useful to look into some used dental X-ray kit, it depends if there's a suitable irradiation cross-section between what the dental units output and what the BGA would require. In any case though, the ZT7 does re-balling too, so I could just do it again if it failed.

 

If I do buy it, I will indeed post about it, good or bad.

 

Simon

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Instructor
Instructor
7,778 Views
Registered: ‎08-14-2007

Re: Spartan-6 for hobby/prototyping

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I don't think you'll be able to get all of the signals routed out in two layers, however you can

stil get a substantial number of I/O's even if you don't route out the innermost balls.  As Bob

pointed out, the outer two rows can easily route out on the top layer with no vias, so you should be

able to get at least two more rows routed out on the bottom (with vias) without running two

traces between vias or pads.

 

There was a discussion at one time about using outer-layer micro-vias to reduce layer count.

These can be fabricated as an extremely thin outer dielectric with a laser used to fuse the

outer copper with the next layer below.  This essentially gives you blind vias that can go to

a 5 mil inner route with no pad on the inner layer.  You'd have to shop around for PCB fab

houses with this capability, but it could end up being cheaper than the 4 additional layers

you'd need to route out a large BGA without it (disclaimer - I have not checked this pricing).

 

With finer pitch BGA's it is often hard to route even with an unlimited number of layers if you

can't go to a smaller via pad, trace and drill size.  That's one reason you don't see many fine-pitch

BGA's designed for PC motherboards, which typically requre a very inexpensive process to

make the board profitable.  Once you've bitten off the BGA part, you may want to look at a larger

BGA package (484-ball?) that is easier to route.

 

-- Gabor

-- Gabor
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Participant sjg69
Participant
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Registered: ‎03-29-2012

Re: Spartan-6 for hobby/prototyping

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Although its good to hear about other ways to solve the problem, one of my goals is to try and stick to the conventional board-fab process, because then prototype-quantity boards can be made at one of the various 'pool' board-houses. I'd come to the conclusion that 1mm BGA  is far-and-away easier than the 0.8mm one as well :)

 

With a 4-mil process, it's pretty easy to bring out all the traces for a '484 on an 8-layer board or a '256 on a 6-layer board. You could probably reduce each of those numbers by 2 if you're willing to compromise on the ground/power planes and/or not route out all the balls, but there'd be consequences...  One of those "for experts only, having tuned for a particular layout/application" things. I'll stick to the more standard way of doing things, I think :) ...As for not routing out all the balls, Xilinx could make this a more viable option if they put the hard-macro connections like the memory controller away from the center of the chip...

 

There are pools that will do a 4-mil trace/space (eg: eurocircuits.com), although I've not found any US-based ones that are comparable in price to the European ones! Given that my copy of ISE is device-locked to an LX45T (it seemed like a good idea at the time :) I'm looking at the '484 part, so it's 8 layer fun...

 

Even if Xilinx couldn't produce a non-BGA version of their larger chips, it might be nice if they could look at making the package friendlier - Analog Devices, TI, etc. all use BGA, but use a slightly larger BGA than technically required, and they miss out balls to aid in routing out the parts, then (at least TI with their star-routing) show you the optimum route for each ball in a series of staged diagrams. I realise there's commercial pressure to reduce package size, but it seems to work ok for other companies to do this. I'm surprised there isn't a use-case for Xilinx' customers too.

 

Still, it is what it is, there's no use moaning about it.

 

Simon.

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