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Observer thedestroyer
Observer
10,814 Views
Registered: ‎07-12-2011

ADC on Spartan 3AN Starter Kit with VHDL

Hello guys :),

 

I'm a beginner with VHDL, and am trying to run the ADC in Spartan 3AN starter kit. I'm using page 71 in the guide:

 

http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf

 

I'm using 2 state machines. One to control the ADC, and the other to control the amplifier.

 

The code took me a few days to write. I think there are many technical errors in the code, but I can't find them. I would appreciate it a lot if you could take a look at the code and tell me whether the code is good enough and complies to the instructions written in the guide.

 

The program is supposed to take the analog signal and show on the vector BarOut a bar graph for the output.

 

I'm using a 50 MHz oscillator.

 

The code is showing warnings that I can't understand. Like: 

 

WARNING:Xst:1710 - FF/Latch <BarOut_0> (without init value) has a constant value of 0 in block <ADCModule>. This FF/Latch will be trimmed during the optimization process.

 

while BarOut is totally dependent on the analog input! and other warnings like:

 

WARNING:Xst:1710 - FF/Latch <BarOut_0> (without init value) has a constant value of 0 in block <ADCModule>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_0> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_3> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_1> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_2> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_6> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_4> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_5> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_9> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_7> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_8> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_VAR_10> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_0> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_1> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_2> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_3> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_4> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_5> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_6> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_7> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_8> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_9> of sequential type is unconnected in block <ADCModule>.

WARNING:Xst:2677 - Node <dataBuffer1_10> of sequential type is unconnected in block <ADCModule>.

 

While all these signals and variables are used!!! I can't really understand how it goes.

 

The simulation shows good results. But the step "map" at "implement design" gives errors.

 

This is my very first serious code. Please tell me what I can do to improve it best.

 

Please find the Code and the Test Bench attached.

 

 

 

 

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27 Replies
Observer thedestroyer
Observer
10,813 Views
Registered: ‎07-12-2011

Re: ADC on Spartan 3AN Starter Kit with VHDL

Test bench:

 

 

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Teacher eteam00
Teacher
10,810 Views
Registered: ‎07-21-2009

starting out on Spartan 3AN Starter Kit with VHDL

While I am too ignorant in VHDL to give you specific advice (you won't have to wait long, don't worry), I have a suggestion for you.  Actually the suggestion is one offered by user bassman to a forum newbie.

 

Suggest you work on a much simpler design in order to learn the language and the tools.  Then work up to the ADC design.  A good starter design is simply to read switches and turn LEDs on and off.  If you can do this, you'll have learned many of the basics -- including instantiating package inputs and outputs.

 

Also, there is much to be learned by reviewing one of the reference designs for the board.  See how device inputs and outputs are declared at the top level in such a design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer thedestroyer
Observer
10,797 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

Thank you for your reply.

 

Actually, I have done tooooo many simple designs already with switches and LEDS and even with the rotating switch. I did counters, shift registers, adders, subtracters, multipliers, dividers, comparators, decoders, frequency dividers, and a lot more.

 

But my problem is: First with timing, Second with understanting the "language" of the User Guide. When I read what users do in forums and other examples, they don't always follow the guides to the latter, and this confuses me. I don't know the limit are for this. And Timing actually is a very confusing concept for me. I don't know when one has to be accurate when they mention, for example, at page 76, Fig. 9-7, the 3 ns difference between the start of AD_CONV and SPI_SCK. How will I set 3 ns while the fastest crystal could do only 50 MHz (20 ns resolution)???

 

 

There are many similar timing problems questions. It would be very nice if someone could take a look at the code, and check the real operation of the circuit with timing and other possible problems, since my simulation is (supposedly) working perfectly, and showing good results, I don't have the least idea on how to check whether I have the "right" circuit for the job + the technical errors (that produce when synthesising) I did due to my noobiness in VHDL :-)

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Scholar joelby
Scholar
10,790 Views
Registered: ‎10-05-2010

Re: starting out on Spartan 3AN Starter Kit with VHDL

If dataBuffer1 and dataBuffer1_VAR are being trimmed, they're never being assigned a value. They are only assigned values in states data_ac1_state and spi_end_wait_state, so check that your UUT is correctly reaching these states while being driven by your test bench (I only had a very quick look at the code, so I might be wrong about the states, but you get the idea - make sure all code paths are being reached).

 

In the timing diagram in figure 9-7, the AD_CONV to SPI_SCK time is probably a minimum time. As long as you leave longer than 3 ns between AD_CONV and the first SPI_SCK, the ADC should return the correct reading. 20 ns should be fine. If you want to be sure, check the data sheet for the ADC for more comprehensive timing data.

 

If you do ever need to produce a faster clock than the system clock, you can use a DCM (digital clock manager) to generate other frequencies (but you might struggle to run fabric logic with a 3 ns period clock in a Spartan-3*).

 

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Observer thedestroyer
Observer
10,786 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

Thank you for your reply!

 

Please find attached the wave form of the simulation. There you'd that dataBuffer and BarOut get the values from "NumToConv" (number to convert), and that all states are working with no problems.


Actually I attached the testBench to show that everything is good in the simulation the way I want it... but I need someone to take a look on the practical aspect of the problem. :-)

 

I will check the manual of the ADC. But, meanwhile, could you guys still take a thorough look on the code? and simulate it?

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Scholar joelby
Scholar
10,782 Views
Registered: ‎10-05-2010

Re: starting out on Spartan 3AN Starter Kit with VHDL

Your code generates loads of warnings about latches that you should take notice of. These may very well cause differences between simulation and the actual FPGA.

 

The problem seems to be the process(downClk6) line, which is being treated as a combinatorial process rather than sequential. You'll need to complete the case statements for all signals mentioned in the warnings, or perhaps turn it into a sequential process using downClk6 as a clock enable (though you'd have to generate one that was only high for one clock cycle).

 

I'm not really sure about the dataBuffer1 signals at this point, but I don't really know much about VHDL.

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Observer thedestroyer
Observer
10,776 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

Thanks for your reply!

 

Ah! I found a bad mistake in my process(downClk6). I had to add if(rising_edge(downClk6)) to detect the rising edge. I fixed that. And I fixed the complaints about some latches. But still, the ones of dataBuffer1 and dataBuffer_VAR and BarOut_0 I can't understant at all :(

 

Please find attached the new edit code. Any new suggestions are highly apprecaited.

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Teacher eteam00
Teacher
10,758 Views
Registered: ‎07-21-2009

code bugs - UPDATE: please ignore!

UPDATE:  The following is mistaken, please ignore!  - Bob Elkind

 

I searched your code for the string "dataBuffer1".  The variable dataBuffer1 is assigned values inside a CASE statement and also assigned values outside the CASE statement in the same process -- with no IF-ELSE to arbitrate between the conflicting assignments.  This is clearly a design bug.

 

For each of the variables you list, you should search your code for assignments for these variables, and make sure you have straightened out when and where these variables are assigned.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher rcingham
Teacher
10,752 Views
Registered: ‎09-09-2010

Re: starting out on Spartan 3AN Starter Kit with VHDL

Your state machine style is rather odd, with 2 registered versions of the 'state variable'.

Either just have a single 'state variable' signal, and do all the work in a single process, or define the 'next' state in a combinational process, and register it to give the 'state variable' which is the selection expression in the case statement.

Some posters to this forum deprecate the 2-process style, but I quite often use it, and I usually name the signals 'this_state', which is registered, and 'next_state', which isn't.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Observer thedestroyer
Observer
9,514 Views
Registered: ‎07-12-2011

Re: code bugs

how come?? dataBuffer1_var is assigned only once (more than once in a loop for each bit)! and then dataBuffer1 gets the value of dataBuffer1 later at some state!

 

Could you please point out the line numbers where you found these bugs?

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Observer thedestroyer
Observer
9,513 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

Thank you for your reply.

 

There are 2 state variables because there are 2 devices to control. First is an amplifier (page 74), and second is an ADC (page 77). Isn't this the right approach, since the amplifier requires a lower frequency?

 

I'm still a beginner. I tried using 2-process style, and it was very hard, since I had many counters. I just want to get this code working so I can start progressing with more professional styles!!

 

Please! tell me what to do with dataBuffer1/dataBuffer1_var, and BarOut_0... I can't understand why these Warnings show up!!!!! I have tried everything I know already.

 

 

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Teacher rcingham
Teacher
9,511 Views
Registered: ‎09-09-2010

Re: starting out on Spartan 3AN Starter Kit with VHDL

"There are 2 state variables because there are 2 devices to control."

There are 2 versions of the state variable for each of your FSMs...

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Teacher eteam00
Teacher
9,510 Views
Registered: ‎07-21-2009

Re: code bugs

how come?? dataBuffer1_var is assigned only once (more than once in a loop for each bit)! and then dataBuffer1 gets the value of dataBuffer1 later at some state!

 

Could you please point out the line numbers where you found these bugs?

I was mistaken.  Apologies, I took instances of dataBuffer1_VAR as dataBuffer1.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer thedestroyer
Observer
9,502 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

Two instances, 1 for current state, one for next state. Do you mean this or something else?

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Teacher rcingham
Teacher
9,498 Views
Registered: ‎09-09-2010

Re: starting out on Spartan 3AN Starter Kit with VHDL

Yes.
You need that if a 2-or-3-process state machine. NOT if a 1-process shate machine.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Observer thedestroyer
Observer
9,496 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

I see what you mean! actually I learned VHDL and state machines from the book "Circuit design with VHDL, 2004, Vaproni (I guess)". In this book state machines are described with 2 processes, but I failed in implementing it because I had combinatorial loops, and I'm too "noob" to implement alternatives to that. So I just switched from 2 processes to one.

 

But this is not a big deal, is it? I mean who cares, 2 more signals and 10 more flip flops (or whatever)!! who cares??? right? it's safer and less error prone for a noob like me :-)

 

Agree?

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Teacher rcingham
Teacher
9,491 Views
Registered: ‎09-09-2010

Re: starting out on Spartan 3AN Starter Kit with VHDL

"Agree?"
No.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Observer thedestroyer
Observer
9,488 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

So sorry to hear that. Let the code now work the easy way, and I promise I'll do it the other way later :-). Maybe you can't see how confused I'm already ^^.

 

 

But could you please check why I'm getting all these warnings? especially with dataBuffer1. with BarOut, I understood it and could fix it. But could that warning ruin the output signal I'm expecting?

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Historian
Historian
9,484 Views
Registered: ‎02-25-2008

Re: ADC on Spartan 3AN Starter Kit with VHDL

Ugh, I don't even know where to begin.

 

Your state machine is a peculiar one-process implemenation of a two-process state machine. All of the variables!

 

Plus there's no initializer or reset for the state machine.

 

Why all of the variables?

 

Rethink your coding style. It's overly complex.

----------------------------Yes, I do this for a living.
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Historian
Historian
10,455 Views
Registered: ‎02-25-2008

Re: ADC on Spartan 3AN Starter Kit with VHDL

oh, there's more to worry about.

 

downClk6 is a gated clock, which is bad.

 

And it's the only thing on the sensitivity list of a process after the comment "amplifier states." (NOTE! Label all of your processes.) But in that process, that signal is never used. So the whole thing is rather confused.

 

Also also: get rid of the "use textio" line. You can't use it in synthesizable code. I note that you've commented out all of the writeline and write statements, which were probably bonked by the synthesizer. You should consider using assertions for this kind of reporting.

----------------------------Yes, I do this for a living.
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Historian
Historian
10,454 Views
Registered: ‎02-25-2008

Re: starting out on Spartan 3AN Starter Kit with VHDL


@thedestroyer wrote:

I see what you mean! actually I learned VHDL and state machines from the book "Circuit design with VHDL, 2004, Vaproni (I guess)". In this book state machines are described with 2 processes, but I failed in implementing it because I had combinatorial loops, and I'm too "noob" to implement alternatives to that. So I just switched from 2 processes to one.

 

But this is not a big deal, is it? I mean who cares, 2 more signals and 10 more flip flops (or whatever)!! who cares??? right? it's safer and less error prone for a noob like me :-)

 

Agree?


Agree? No. The two-process state machine is a leftover from the bad old days (like literally 20 years ago) when synthesis tools were stupid and people lived near the water. All modern synthesis tools handle the single synchronous-process state machine just fine.

----------------------------Yes, I do this for a living.
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Observer thedestroyer
Observer
10,451 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

Thank you so much for your time.

 

I think I stil need to read tons of books about VHDL :-)

 

I'll try to fix all that. I'll do my best :-)

 

P.S.: This is my very first serious code I ever write with VHDL :-)

 

Regards :-)

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Teacher rcingham
Teacher
10,438 Views
Registered: ‎09-09-2010

Re: starting out on Spartan 3AN Starter Kit with VHDL

"I think I stil need to read tons of books about VHDL"

One good one will do. I like Peter J. Ashenden's 'The Designer's Guide to VHDL', but it might not be to your taste.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Observer thedestroyer
Observer
10,432 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

I'm reading it actually already. I have read already 100 pages of that. Its problem is that it's very very theoretical, and it doesn't distinguish between synthesisable and non-synthesisable stuff.

 

But since every professional one prefers it, then I'll continue with it, in hope of becoming as good as they are :D

 

Thanks for the advice :-)

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Historian
Historian
10,428 Views
Registered: ‎02-25-2008

Re: starting out on Spartan 3AN Starter Kit with VHDL


@thedestroyer wrote:

I'm reading it actually already. I have read already 100 pages of that. Its problem is that it's very very theoretical, and it doesn't distinguish between synthesisable and non-synthesisable stuff.

 

But since every professional one prefers it, then I'll continue with it, in hope of becoming as good as they are :D

 

Thanks for the advice :-)


The XST manual is pretty clear on which constructs are synthesizable and which are not.

----------------------------Yes, I do this for a living.
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Observer thedestroyer
Observer
10,424 Views
Registered: ‎07-12-2011

Re: starting out on Spartan 3AN Starter Kit with VHDL

After investigating and reading many "modern" state machines, I changed mine. I guess you're gonna like the new style ^^

 

You're right! the new style is waaaaaaaaaaaaaay easier to implement :D

 

I'm facing a small problem. The code is complaining that dataBuffer2_13 (last bit) is never used, although it's being used the same way dataBuffer1 is used. Could you please tell me something about it if you could understand it?

 

Thank you for the advice, again :-)

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9,599 Views
Registered: ‎02-18-2013

Re: starting out on Spartan 3AN Starter Kit with VHDL

is your problem solved ?

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