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Newbie johnny.lee
Newbie
428 Views
Registered: ‎08-06-2018

About SPARTAN 3-AN (3S50AN) FPGA OF UMC (0.11um process) SIMULATION LIBRARY.

Dear Sir or Madam.

 

I have one questions of when I use simulation of SPARTAN 3-AN (3S50AN) FPGA OF UMC (0.11um process).

 

I use a ISE 14.7 which have a unisims library in 'C:\Xilinx\14.7\ISE_DS\ISE\verilog\src\unisims' directory.

 

That directory have a SPI_ACCESS.v file that has a revision History.

 

But this file late update was 03/23/11. Is it can possible to support UMC(0.11 um process) ?

 

I think that SPI_ACCESS.v file very more old then UMC update time for FPGA simulation(UNISIMS).

 

If you have any questions, feel free ask to me. So I want to many reply from this forum.

 

Thank so much.

* From South Korea in VERY HIGH HIGH SUMMER^^.

 

 

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Xilinx Employee
Xilinx Employee
394 Views
Registered: ‎06-30-2010

Re: About SPARTAN 3-AN (3S50AN) FPGA OF UMC (0.11um process) SIMULATION LIBRARY.

sorry i don't understand the reference to UMC 0.11um process, are you referring to the FPGA process?

That is not really relevant for the simulation of an IP, all that is doing is showing the functionality of the IP.
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