11-15-2011 06:33 PM
I want an FPGA input to monitor fast changing signal with up to 6V amplitude. The circuitry before FPGA pin will consist of resistor divider (to reduce 6V to 1.8V) with a capacitor parallel to one of divider's resistor to pass high frequency signal. This capacitor together with parasitic capacitance of the FPGA will make another voltage divider.
FPGA input will be used in HSTL 1.8V mode. Unfortunately, Spartan-6 has no clamp diode to VCCIO in this mode. If I known the minimal possible capacitance of the FPGA pin then I would be able to chose a capacitor value for the divider to make sure that the voltage on FPGA input will not exceed the absolute maximum 4.1V. This will eliminate the need of external clamp diode to VCCIO.
For example, if I choose 4.7pF capacitor for the divider, this will require that the capacitance of FPGA pin should be equal or larger then 2.2pF in order to divide 6V to 4.1V and less. I'm 99% sure FPGA pin capacitance always higher then 2.2pF. Spartan-6 IBIS file lists 5.63pF as the minimal pin capacitance.
The question is: can I be sure that FPGA pin parasitic capacitance always >= 2.2pF? Or this is too risky and I should add an external clamp diode?
Conditions: pin is configured as HSTL 1.8V input only, or FPGA is not configured, or FPGA is unpowered.
11-15-2011 06:41 PM - edited 11-15-2011 06:42 PM
Why not use the IBIS models for the various package pins and input buffer, run circuit simulations of your divider, and work through the range of possible values for a "can't fail" solution?
-- Bob Elkind
11-16-2011 08:52 AM
The IBIS model is a specification. It is, what the device is. Unlike other vendors, who test a few parts to extract an IBIS model, Xilinx performs extractions, and spice models, to predict what the IBIS models are for all process, voltage, and temperature conditions. We then verify the models when we do our verification and validation before a product goes to production.
So, if IBIS says 5.63pf, then that is what it is. Look at the fast/strong corner, and the slow/weak corner, and you get the min and max values. Although, I doubt the capacitance changes at all over process, voltage and temperature.
11-17-2011 06:15 AM
" Unlike other vendors, who test a few parts to extract an IBIS model..."
11-17-2011 07:30 AM
I would go further, most vendors pay someone else to take their devices and test a few, and produce the models.
It is "standard practice" and it is a disservice to customers as it is an inferior method to developing the models.
05-06-2016 08:42 PM
Is the pin capacitance the same for the pins that can also be VRef inputs ?
In altera Cyclone IV datasheet, they SPECIFICALLY note that the pin capacitance on those is 3x the normal pin capacitance (21pf vs 7pF) and that they shouldnt be used if timing is important.
Should i take this into account and avoid VRef pins for high speed clocks and such on a Spartan6 ?
05-07-2016 10:32 AM
Vref capable io pins cin when not programmed to be vref pins, is the nominal specified.
Clocks in any event should use the clock capable io pins.