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kenneth_lee
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Registered: ‎07-26-2010

Analog Capture Circuit!

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Hi, i facing some problem on my analog capture circuit of Spartan 3E - 1600 board.

I have follow all the instruction and timing diagram of the user guide menu but i dont understand why the output i get from the SPI_MISO to LCD to show out the values keep giving me "FFF3" for both Vin A and B.

The way i output the 14-bits for channel 0 and 1to LCD is like that:

Exp:

i separate the 14 bits output from each channel by every 4bits in order to form a hexadecimal values to show in LCD:

such as XXXX | XXXX | XXXX | XX00 , the reason i put 2 zeros in begining part is to let the SPI_MISO data able to divide every 4 digits to show in LCD. unfortunately, i keep obtain this answer from my LCD "FFF3" which means that the SPI_MISO output all in '1'. Can any tell me why ?

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bassman59
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Registered: ‎02-25-2008

 


@kenneth_lee wrote:

Dear Bassman59,

MAy i know that what you means about this ----- "All of your synchronous processes have signals other than the clock on their sensitivity lists -- that's wrong." ??? Can you list down which part on my code!!! thanks.

Regarding the simulation result, for the both Programmable Gain Settings for Pre-Amplifier and ADC, the timing is correct unless the datasheet mention that "at least 50ns" but i put more than that!


 

The question about sensitivity lists has been answered. Now go buy a proper VHDL textbook, like Ashenden's.
As for the simulation: did you create a model of the ADC, that takes a real number as an input, and when clocked appropriately gives a serial bitstream that represents the analog input? If not, you should. Otherwise, you haven't simulated your circuit.

 


 

For "Why is FPGA_INIT_B a signal?", actuyally i just disable it only as mention in the datasheet, and it's locate at pin T3.

 


 

 

The FPGA's INIT_B signal is part of the configuration logic, and has nothing to do with your design after configuration. It should not be in the design at all.

 

 


Now, i found another problem that is i check out the Programmable Gain Settings for Pre-Amplifier, as list in my code i assign "00010001" (Gain=-1) but i check out the AMP_DOUT signal output from the "LTC 6912-1 AMP" it show me all "1" that's means that the gain is not set. Why this happen ? If i compare with my simulation result it was satisfy the timing, why the SPI_MOSI unable input data into the Programmable Gain Settings for Pre-Amplifier???

 

 


Did you look at all of the signals with an oscilloscope?

 

----------------------------Yes, I do this for a living.

View solution in original post

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kenneth_lee
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Registered: ‎07-26-2010

Can anyone help me on this problem that i facing now please?

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bassman59
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Registered: ‎02-25-2008

 


kenneth_lee wrote: unfortunately, i keep obtain this answer from my LCD "FFF3" which means that the SPI_MISO output all in '1'. Can any tell me why ?

 

Maybe the ADC input is at the positive rail?

Maybe the ADC isn't working?

Maybe your code doesn't work?

Did you simulate? Are you meeting timing?

----------------------------Yes, I do this for a living.
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kenneth_lee
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Registered: ‎07-26-2010

Dear sir,

Thanks for reply, Actualy even i havent input any analog signal in the VinA or VinB the the SPI_MISO already give me such values all in '1' that's why i keep obtain FFF3 for both input channel. i think high percentage is that ADCV is not working as well, and even they can accept my analog inpu from VinAorB although i supply signal on it. But i keep checking my code and simulation test bench result all the timing should be fine. May be i attach here my code can u please help me take a look whether i make any mistake on that!!!! actually this code i provide here i obtain from the forum and i modify abit on it, before that i also write out my own code for my ADC but it doesnt working and i spend a lot of time on it but still the same then i read out the forum and i found that someone post out the code and they say shoukd be working but after i using their code the answer still the same as mine code so can u please help me out have a look on it and find out which step i wrong taken, your help will be appreciate for me. Thanks.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADC is
Port (   
     AMP_SHDN : out std_logic:='1';      ---AMP_SHDN
     AMP_CS : out  STD_LOGIC:='1';         --AMP_CS
     SPI_MOSI : out  STD_LOGIC:='0'; -- amp      ---SPI_MOSI
           SPI_SCK : out  STD_LOGIC:='0';        ---SPI_SCK
     SYSCLK : in  STD_LOGIC;        --SYS_CLK
     SPI_MISO : in std_logic; --adc     --SPI_MISO
     AD_CONV : out  STD_LOGIC:='0'; --adc       ---AD_CONV
      
     SWCS : in std_logic;         --SW_AMPCS (FOR START GAIN TRANSFER)
     start_conv : in  STD_LOGIC;      --CONVERT (FOR START ADC CONVERT)
    
     sample: out std_logic:='0';     
     ADC1 : out std_logic_vector(13 downto 0) := (others => '0'); --FOR CHANNEL 0 to LCD
     ADC2 : out std_logic_vector(13 downto 0) := (others => '0');  -- FOR CHANNEL 1 to LCD
     SPI_SS_B: out std_logic;       --U3 Pin
     DAC_CS: out std_logic;       --N8
     FPGA_INIT_B: out std_logic      --T3 
       
     );
end ADC;

architecture Behavioral of ADC is
        
 type state_type1 is (IDLE1,IDLE, START,START2,HI,HI_DUMMY,LO,LO_DUMMY,FINE,OK);
 type state_type2 is (IDLE_AD, START_AD,HI_AD,LO_AD,FINE_AD);
   signal Gainstate : state_type1;
 signal ADCstate : state_type2;
 signal counter1,counter2 : integer range 0 to 1500000; 
-- signal ADC2 : std_logic_vector (13 downto 0):=(OTHERS=>'0');
 signal bit_count: std_logic_vector (4 downto 0):=(OTHERS=>'0');
 signal gain_temp: std_logic_vector (7 downto 0):="00010001";
 SIGNAL iAMPSHDN,iAMPCS: std_logic:='1';
 signal iSPIMOSI,iSPICLK,iADCONV,isample: std_logic:='0';
 signal iEnable: std_logic:='0';
 signal SCK1,SCK2: std_logic:='0';


begin

SPI_SCK<= SCK1 when iEnable='0' else
    SCK2 when iEnable='1';

DAC_CS <= '1';
SPI_SS_B <= '1';
FPGA_INIT_B <= '1';

process(SYSCLK,SWCS)
begin

 if SYSCLK'event and SYSCLK ='0' then

  case Gainstate is
   when IDLE1 => if SWCS = '1' then
        Gainstate <= IDLE;
         else
        Gainstate <= IDLE1;
        AMP_SHDN <= iAMPSHDN;  --initial AMP_SHDN assume '1' RESET
        AMP_CS <= iAMPCS;   --initial AMP_CS active low so remain at high state
         end if;
        
   when IDLE =>
     AMP_SHDN <= '0';     --no shutdown
     SCK1 <= iSPICLK;       --SPI_SCK
     AMP_CS <= '1';      --AMP_CS still remain at high state
     SPI_MOSI <=iSPIMOSI;       --SPI_MOSI for gain initial is 0
     counter1 <= 0;-- 0;
     Gainstate <= START;               
      
   when START =>
    Gainstate <= LO_DUMMY; 
    bit_count <= "00000"; --:=0;
    AMP_CS <= '0';      
    gain_temp <= "00010001";     --INPUT Gain Values
    
   when START2 =>
    Gainstate <= HI; 
    SPI_MOSI <= gain_temp(7);

   when HI => 
    if counter1 = 2 then--2 then
     Gainstate <= HI_DUMMY;
    else
     SCK1 <= '1';      
         counter1 <= counter1 +1;
     Gainstate <= HI;
    end if;   

   when HI_DUMMY =>
     bit_count <= bit_count + 1; --:= bit_count + 1;
     Gainstate <= LO;
     counter1 <=0;--0;
     SCK1 <= '1'; 
     gain_temp(7 downto 1) <= gain_temp(6 downto 0);
     
   when LO =>
    if bit_count = "01000" then --8 then
     Gainstate <= FINE; 
    
    elsif counter1 = 2 then --2 then
     SPI_MOSI <= gain_temp(7);
     Gainstate <= LO_DUMMY;
    else
     SCK1 <= '0';
     counter1 <= counter1 +1;
     Gainstate <= LO;
    end if; 
     
   when LO_DUMMY =>
     
     counter1 <=0;
     SCK1 <= '0';
     Gainstate <= HI;  
    
   when FINE =>
   
     AMP_CS <='1';
     SCK1 <= '0';
     SPI_MOSI <= '0';
     iEnable<='1';
     Gainstate <= OK;
   when OK =>
     AMP_CS <='1';
     SCK1 <= '0';
     SPI_MOSI <= '0';
     Gainstate<=OK;
  end case;
 end if;
end process;
  
process(SYSCLK,iEnable,start_conv)
begin

 if SYSCLK'event and SYSCLK ='1' then
 
 case ADCstate is
 
   when IDLE_AD =>
     if iEnable='1' then
     
   --  AMP_CS <= '1';
     SCK2 <= '0';
     AD_CONV <= iADCONV;
     sample <=isample;               
     
     if start_conv = '1' then
      ADCstate <= START_AD; 
     else
      ADCstate <= IDLE_AD;
     end if;
     
     else
      ADCstate<=IDLE_AD;
     end if;
       
   when START_AD =>
     SCK2 <= '0';
     AD_CONV <= '1';
     counter2 <= 0;--0;
     sample <='0';
     ADCstate <= HI_AD;  
    
   when HI_AD => 
     SCK2 <= '1';
     AD_CONV <= '0'; 
     counter2 <= counter2 +1; 
     sample <='0';
     ADCstate <= LO_AD;
    
    
   when LO_AD =>
     SCK2 <= '0';
     if counter2 = 3 then  --20
       ADC1(13)  <=  not SPI_MISO;
     elsif counter2 = 4 then  
       ADC1(12)  <= SPI_MISO;
     elsif counter2 = 5 then
       ADC1(11)  <= SPI_MISO;
     elsif counter2 = 6 then
       ADC1(10)  <= SPI_MISO;
     elsif counter2 = 7 then
       ADC1(9)  <= SPI_MISO;
     elsif counter2 = 8 then
       ADC1(8)  <= SPI_MISO;
     elsif counter2 = 9 then
       ADC1(7)  <= SPI_MISO;
     elsif counter2 = 10 then
       ADC1(6)  <= SPI_MISO;
     elsif counter2 = 11 then
       ADC1(5)  <= SPI_MISO;
     elsif counter2 = 12 then
       ADC1(4)  <= SPI_MISO;
     elsif counter2 = 13 then
       ADC1(3)  <= SPI_MISO;
     elsif counter2 = 14 then
       ADC1(2)  <= SPI_MISO;
     elsif counter2 = 15 then
       ADC1(1)  <= SPI_MISO;
     elsif counter2 = 16 then
       ADC1(0)  <= SPI_MISO;  
     elsif counter2 =  19 then  --20
       ADC2(13)  <=  not SPI_MISO;
     elsif counter2 = 20 then  
       ADC2(12)  <= SPI_MISO;
     elsif counter2 = 21 then
       ADC2(11)  <= SPI_MISO;
     elsif counter2 = 22 then
       ADC2(10)  <= SPI_MISO;
     elsif counter2 = 23 then
       ADC2(9)  <= SPI_MISO;
     elsif counter2 = 24 then
       ADC2(8)  <= SPI_MISO;
     elsif counter2 = 25 then
       ADC2(7)  <= SPI_MISO;
     elsif counter2 = 26 then
       ADC2(6)  <= SPI_MISO;
     elsif counter2 = 27 then
       ADC2(5)  <= SPI_MISO;
     elsif counter2 = 28 then
       ADC2(4)  <= SPI_MISO;
     elsif counter2 = 29 then
       ADC2(3)  <= SPI_MISO;
     elsif counter2 = 30 then
       ADC2(2)  <= SPI_MISO;
     elsif counter2 = 31 then
       ADC2(1)  <= SPI_MISO;
     elsif counter2 = 32 then
       ADC2(0)  <= SPI_MISO;
     else
       sample <='0';
     end if;

     if counter2 = 34 then
       ADCstate <= FINE_AD; 
     else
       ADCstate <= HI_AD;
     end if;
  

   when FINE_AD =>
     ADCstate <= IDLE_AD;
     counter2 <= 0;
     SCK2 <= '0';
     AD_CONV <= '0';
     sample <= '1';
     
   when others =>  
     SCK2 <= '0';
     AD_CONV <= '0'; 
  --   AMP_CS <= '1';
  --   SPI_MOSI <='0';
     ADCstate <= IDLE_AD;
     
  end case;
 end if;
end process;

end Behavioral;

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bassman59
Historian
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Registered: ‎02-25-2008

Does that code meet timing? The mux in the LO_AD state is pretty big and ugly (and there's a MUCH better way to do the shift register).

 

You say you simulated it. Is your test bench correct?

 

All of your synchronous processes have signals other than the clock on their sensitivity lists -- that's wrong.

 

Port comments that just repeat the signal name are useless.

 

Why is FPGA_INIT_B a signal?

 

 

 

 

----------------------------Yes, I do this for a living.
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kenneth_lee
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Registered: ‎07-26-2010

Dear Bassman59,

MAy i know that what you means about this ----- "All of your synchronous processes have signals other than the clock on their sensitivity lists -- that's wrong." ??? Can you list down which part on my code!!! thanks.

Regarding the simulation result, for the both Programmable Gain Settings for Pre-Amplifier and ADC, the timing is correct unless the datasheet mention that "at least 50ns" but i put more than that!

 

For "Why is FPGA_INIT_B a signal?", actuyally i just disable it only as mention in the datasheet, and it's locate at pin T3.

 

Now, i found another problem that is i check out the Programmable Gain Settings for Pre-Amplifier, as list in my code i assign "00010001" (Gain=-1) but i check out the AMP_DOUT signal output from the "LTC 6912-1 AMP" it show me all "1" that's means that the gain is not set. Why this happen ? If i compare with my simulation result it was satisfy the timing, why the SPI_MOSI unable input data into the Programmable Gain Settings for Pre-Amplifier???

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roym
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Registered: ‎07-30-2007

>MAy i know that what you means about this ----- "All of your synchronous processes have signals other than the clock on >their sensitivity lists -- that's wrong." ??? Can you list down which part on my code!!! thanks.

 

This means that the line:

 

process(SYSCLK,iEnable,start_conv)

 

should be

 

process(SYSCLK)

 

The signal sensitivity list is used to specify which signals should cause the process to be re-evaluated.  You only want the states to change on the positive edge of the clock so that should be the only signal listed.

 

 http://www.gmvhdl.com/process.htm

 

-R




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kenneth_lee
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May i know that if the timing all correct what is the others possible causes that may cause me unable to output the SPI_MOSI signal into the Programmable gain setting ? Since i check out the AMP_DOUT from pin E18 it show me all '1' which means that my gain setting "00010001" cannot reach the  LTC 6912-1 AMP SPI control interface. Or is it my code wrong ? But regarding the datasheet the LTC 6912-1 AMP SPI control interface will read the input data during rising edge of the SPI_SCK and i also meet the minimum timing before reach the 30ns, all of that i have follow exactly (except i put more than the minimum timing requirement) but i check out the test bench result it should be ok. So,what is the problem? is it even others signal such as SPI_SCK also unable input to the system??? but i cant check it out practically. So, please help, what should i do? Thanks.

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kenneth_lee
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Now, i Solve out the Gain setting already from the AMP_DOUT it show me a correct result! Tha's means now the gain have been set, and i think is ok for first part but now my ADC part the SPI_MISO that input to the FPGA are not correct? So, i think i make some mistake on ADC part !!!! But, i'm still don't know which part i going wrong ! Any expert can help me out? Thanks in advance !

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bassman59
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Registered: ‎02-25-2008

 


@kenneth_lee wrote:

Dear Bassman59,

MAy i know that what you means about this ----- "All of your synchronous processes have signals other than the clock on their sensitivity lists -- that's wrong." ??? Can you list down which part on my code!!! thanks.

Regarding the simulation result, for the both Programmable Gain Settings for Pre-Amplifier and ADC, the timing is correct unless the datasheet mention that "at least 50ns" but i put more than that!


 

The question about sensitivity lists has been answered. Now go buy a proper VHDL textbook, like Ashenden's.
As for the simulation: did you create a model of the ADC, that takes a real number as an input, and when clocked appropriately gives a serial bitstream that represents the analog input? If not, you should. Otherwise, you haven't simulated your circuit.

 


 

For "Why is FPGA_INIT_B a signal?", actuyally i just disable it only as mention in the datasheet, and it's locate at pin T3.

 


 

 

The FPGA's INIT_B signal is part of the configuration logic, and has nothing to do with your design after configuration. It should not be in the design at all.

 

 


Now, i found another problem that is i check out the Programmable Gain Settings for Pre-Amplifier, as list in my code i assign "00010001" (Gain=-1) but i check out the AMP_DOUT signal output from the "LTC 6912-1 AMP" it show me all "1" that's means that the gain is not set. Why this happen ? If i compare with my simulation result it was satisfy the timing, why the SPI_MOSI unable input data into the Programmable Gain Settings for Pre-Amplifier???

 

 


Did you look at all of the signals with an oscilloscope?

 

----------------------------Yes, I do this for a living.

View solution in original post

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kenneth_lee
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First of all, thanks for the advise from . I will try out what you mention.

 

Now, i found another problem, i think most probably is main things that cause the ADC cannot run. I found that my Amplifier gain is not properly set. And the main problem is the SPI_MOSI serial data that i output from the FPGA cannot reach the Amplifier? why this happen. (i double check my pin is correct and also the timing). For example i assign a constant  "0" into the SPI_MOSI output but while i check the AMP_DOUT i doesnt show me all '0' but it show me "00010001" what means that the first bit it read is 1 follow by 00010001???? why?

Regarding the datasheet mention the amplifierwill capture the SPI_MOSI serial data during rising edge and output the "data being capture" at falling edge. but i found that it seem like doesnt work? Why? Why my SPI_MOSI serial data cant send to amplifier gain???

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kenneth_lee
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hi, may i know that is it any setting that i need to be take notes on my FPGA board (Exp: jumper setting, board setting ......etc) in order to let the ADC working, because i found that my SPI really not function at all ?

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kenneth_lee
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Yahooooo......finally i solve my ADC already, thanks for those giving  me support withnin this forum. ^.^ Thank you ...Thank you.

But, this really take me a long time to troubleshoot. >.<

Once more time, thanks for those provide me the suggestion and solution and pls forgive my stupid. Thank you.

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kenneth_lee
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Registered: ‎07-26-2010

Dear sir,

May i know that if i create my ADC controller using picoblaze but i would like to do another project that to control my motor speed using microblaze so that i would like to input my ADC output signal (ADC1,ADC2 as shown in code) to my microblaze which serve as input to the microblaze is that possible???

if yes do u have any example that may help me to do that?

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rourabpaul
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Registered: ‎08-13-2010
what the exat mistake you have done??
pls share
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eteam00
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Registered: ‎07-21-2009

FYI: Kenneth Lee hasn't logged in for over 3 months.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
rourabpaul
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is it possible to get any information such that email id of Kenneth Lee from Forum moderator??

 

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eteam00
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Suggest you send him a private message using the message facility in these forums.  Click the envelope icon just below the grey Search button near top right of page.  If Mr. Lee wants to respond, he will.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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kenneth_lee
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Hmm....Sorry for late reply...this project i have done few months ago. i'm not sure that i'm still remember or not ! Regarding the problem that i face last time, if i not mistaken actually last time the problem that i face is because i combine both the amplfier gain setting and the ADC capture program together (actually should be no problem, you can do it also). However, i found that i make some misstake during the gain setting which is the first stage, therefore i cause the whole system going to wrong that's why the ADc cannot work well.

So, i advice to you is :

1.first check the gain setting  by checking the output from the "AMP_DOUT" to confirm that the gain setting that read by the is correct.(you can output the signal to the LED to verify the answer)

2.after make sure the gain setting is correct then do the second part that is for the ADC capture.

 

So, if i not mistaken the main mistake that i make last time is the gain setting part. So, try double check your gain setting first. After make sure it is right then combine both the ADC capture both together in a one program.

 

Hope this may help you. :smileyhappy:

 

 

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rago822
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Registered: ‎12-16-2010

can u provide me with the final code??????

Tags (1)
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rourabpaul
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the output SPI_SCK is in our hand,

what should be the rang of SPI_SCK ?

can we equate it with system clock(50 MHz)?

 

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bassman59
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@rourabpaul wrote:
the output SPI_SCK is in our hand,

 


 

 

I've got the whole world in my hand!


 

what should be the rang of SPI_SCK ?

 


 

 

Dunno, what says the data sheet for the thing to which the signal is connected?

 

 


 

can we equate it with system clock(50 MHz)?

Depends, what says the data sheet for the thing to which the signal is connected?

 

----------------------------Yes, I do this for a living.
rago822
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Registered: ‎12-16-2010

Hi

I have the same problem as Kenneth has faced in the begining. The output I get on the display always seems to be 3fff. I tried the method he used by checking the amp_dout as the gain settings might be wrong. But I dont know how to proceed further to correct it. Kindly help me.

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rago822
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Registered: ‎12-16-2010

I am trying out with the same code that kenneth has used except I am disbling the other devices like fpga_init_b in the toplevel.

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wouterdevriese
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Registered: ‎03-15-2011

I'm also struggeling with the VHDL-code of the ADC..
Is it possible to take a look at your working code?

greetings!

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