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Visitor fpga35man
Visitor
6,416 Views
Registered: ‎04-02-2015

Atlys board HDMI problem with EDID or Atlys_HDMI_PLB_demo.zip

 

 

First, I ask to be excused.

I alreay wrote similiar post message 6 month ago. but I can't and post again.

 

I tested with EDK HDMI Demo(using ISE 12.3 ) like below in Atlys.

https://reference.digilentinc.com/atlys:atlys:atlys

 

But , I don’t have good performance with HDMI in(PC or camera) , HDMI out(Monitor).

I was trying to find the reason in xilinx forum, but still don’t know why.

 

I speculate between two things : Bad source(attached file EDK HDMI Demo : atlys_hdmi_pld_demo.zip) or EDID translation.

 

I followed @joelby advice about EDID. I'm using HDMI DDC pass-through and have set the corresponding pins in the FPGA to high impedance as suggested in the link.

Note that if you are using HDMI DDC pass-through, you will need to set the corresponding FPGA pins (C13 and A13, D9 and C9) to high impedance in your constraints file or else they will load the bus.

(This is notification in https://joelw.id.au/FPGA/DigilentAtlysResources for EDID setting)

 

for e.g.

 

In Design( OBUFT or bufif1)

  • OBUFT #(

.DRIVE(12), // Specify the output drive strength

.IOSTANDARD("DEFAULT"), // Specify the output I/O standard

.SLEW("SLOW") // Specify the output slew rate

) OBUFT_inst2 (

.O(TMDS_TX_SDA), // Buffer output (connect directly to top-level port)

.I(0), // Buffer input

.T(1) // 3-state enable input

);

 

  • bufif1(TMDS_TX_SDA , 0 , 0);

 

In UCF

 

NET "TMDS_TX_SCL" LOC = D9;

NET "TMDS_TX_SDA" LOC = C9;

 

NET "TMDS_TX_SCL" IOSTANDARD = I2C;

NET "TMDS_TX_SDA" IOSTANDARD = I2C;

 

 

I am continue to waste my time to find a method over 6 months.

Please tell me  how can I operate with HDMI DEMO(EDK)

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3 Replies
Scholar joelby
Scholar
6,108 Views
Registered: ‎10-05-2010

Re: Atlys board HDMI problem with EDID or Atlys_HDMI_PLB_demo.zip

What exactly do you mean by "don't have good performance"? Does the demo work at all?

 

I'm only vaguely familiar with the HDMI PLB Demo (having skimmed over the data sheet a few minutes ago) but it appears that it (correctly) emulates an I2C ROM in order to send EDID information to the HDMI source. You should NOT need to tri-state these pins or do anything like that - it's not even clear how you would, as they would conflict with the I2C device, which is also using those pins - as long as you've correctly set your board's jumpers according to the data sheet.

 

 

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Visitor fpga35man
Visitor
6,079 Views
Registered: ‎04-02-2015

Re: Atlys board HDMI problem with EDID or Atlys_HDMI_PLB_demo.zip

first , thank you for your reply.

I hope you understand my short English skill.

 

What exactly do you mean by "don't have good performance"? Does the demo work at all?

 => Good permance mean demo work correctly ( HDMI in : 1280*720 Camera , HDMI out : Monoitor)

 

 Your reply

You should NOT need to tri-state these pins or do anything like that - it's not even clear how you would, as they would conflict with the I2C device, which is also using those pins

 

=> I  have tri-state tese pins because you note that if you are using HDMI DDC pass-through, you will need to set the corresponding FPGA pins (C13 and A13, D9 and C9) to high impedance in your constraints file or else they will load the bus.

I search a lot of advice in forum. as result of that I  draw a decision that tri-state = high impedance in UCF.

 

you've correctly set your board's jumpers according to the data sheet.

=> Datasheet for HDMI_demo_project only have  "8) Once the program has downloaded, attach a display device to HDMI OUT port J2 and a video source to HDMI IN port J3. Ensure that jumpers 6,7 and 8 are not shorted." for board's jumper.

 

I want to know whether (a step 8 :jumpers 6,7 and 8 are not shorted) is correct set or not.

Please tell me concretely good set for EDID  DDC pass-throuh if it is not correct.

 

 

 

 

 

 

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Scholar joelby
Scholar
6,076 Views
Registered: ‎10-05-2010

Re: Atlys board HDMI problem with EDID or Atlys_HDMI_PLB_demo.zip

EDID passthrough is not applicable to the Atlys_HDMI_PLB demo, because it implements its own EDID ROM on the FPGA (including tri-stating). You want to ensure that the HDMI input port's SDA/SCL pins are connected to the FPGA.

 

I can't reach the Digilent web site at the moment so I'm not sure which HDMI input port this design uses, but to be safe you could enable them both:

 

onboard HDMI IN1 (PMODA):
- Type A connector, marked as J1, on side with USB connectors.
- Make sure JP4 is connected

- JP2 (marked as SCA/SCL) has two jumpers (on a 2x2 header) and these should both be configured horizontally (in the same direction as the "ATLYS" text. On a new board, they may be installed incorrectly (vertically)

 

onboard HDMI IN2
- Type A connector, marked as J3, between audio connectors and Ethernet
- Connect JP8

- Disconnect JP6 and JP7

 

 

 

 

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