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Newbie jdraper12
Newbie
3,974 Views
Registered: ‎01-16-2018

Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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Hey everyone.

I've just started learning VHDL and I decided to design a 4-bit universal shift register as a challenge. I want to approach the component structurally, as opposed to behaviourally.

I've got pretty much all of the system design done (multiplexers, flip-flops and top module all compile fine), however  the register seems to only be able to parallel load, and shifting left or right just doesn't seem to have a response. I was hoping that someone on here could have a read through my code and see if there's anything glaringly obvious missing or if I've made any rookie errors? I've included my VHD files and an annotated schematic detailing my system design.

Any help would be really appreciated! Cheers in advance.




Annotation.jpg
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Scholar jmcclusk
Scholar
5,175 Views
Registered: ‎02-24-2014

Re: Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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your problem is simple..   outnet and colnet are the same wires!!  but you've separated them in the VHDL..   your solution to this homework problem is to delete outnet, and just use colnet everywhere, including driving the Q outputs.    

Don't forget to close a thread when possible by accepting a post as a solution.
7 Replies
Scholar jmcclusk
Scholar
5,176 Views
Registered: ‎02-24-2014

Re: Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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your problem is simple..   outnet and colnet are the same wires!!  but you've separated them in the VHDL..   your solution to this homework problem is to delete outnet, and just use colnet everywhere, including driving the Q outputs.    

Don't forget to close a thread when possible by accepting a post as a solution.
Newbie jdraper12
Newbie
3,933 Views
Registered: ‎01-16-2018

Re: Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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Ah I see what you mean now! The output of FFA should be setting the input for MuxB and so on, but I've excluded it in my OR statement... Thought that logic was wrong! Thanks a lot I'll implement this and let you know if it's been solved.

 

You're right about this being a homework problem hahah but it's already submitted RIP, this problem was just really nagging me though.

 

Can you see any other problems, like any bad coding practice or poor logic?

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Scholar jmcclusk
Scholar
3,929 Views
Registered: ‎02-24-2014

Re: Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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The coding style is obsolete..   not very well done..   a 4 input mux should look like this:

 

mux_out <=  input_a when sel="00" else

                     input_b when sel="01" else

                     input_c when sel="10" else

                     input_d;

 

Always use ieee.numeric_std.all    and not the old deprecated unsigned packages.

Don't forget to close a thread when possible by accepting a post as a solution.
Newbie jdraper12
Newbie
3,923 Views
Registered: ‎01-16-2018

Re: Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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Alright cheers! I'll follow that advice. I'm using Xilinx 10.3 maybe it includes the obsolete ones by default?

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Xilinx Employee
Xilinx Employee
3,794 Views
Registered: ‎06-30-2010

Re: Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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If possible please move to the latest version of ISE so 14.7
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Newbie jdraper12
Newbie
3,788 Views
Registered: ‎01-16-2018

Re: Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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I would, however uni insists to use 10.3 for its live testbench feature
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Scholar jmcclusk
Scholar
3,761 Views
Registered: ‎02-24-2014

Re: Attempting Universal Shift Register in VHDL for Spartan 3 Implementation

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Please tell your university instructor that they MUST move the tools from ISE to Vivado without delay.   No university graduate with ISE experience will be employable.   Vivado experience is a hard requirement for new hires today.    Vivado is also a far superior tool, and doesn't even need a license for simulation and webpack class devices.   

Don't forget to close a thread when possible by accepting a post as a solution.