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Visitor
Visitor
7,276 Views
Registered: ‎09-06-2012

BUFIO2 use_doubler => true error ?

Can anyone help me by explaining what is wrong? Did I misunderstand UG382, or did I code it wrong?

 

I can not see any difference when outputting clk_in1_div using the following codes:

V1_input:

	clk1im_BUFIO2: BUFIO2 generic map (	-- buforuję zegar z wejścia, zeby taktować dane wejściowe. Przy okazji go odwracam
      DIVIDE			=> 7,				-- DIVCLK divider (1-8)
      DIVIDE_BYPASS	=> FALSE,		-- Bypass the divider circuitry (TRUE/FALSE)
      I_INVERT			=> FALSE,		-- Invert clock (TRUE/FALSE)
      USE_DOUBLER		=> TRUE			-- Use doubler circuitry (TRUE/FALSE)
   )port map (
      DIVCLK			=> clk_in1_div,		-- 1-bit output: Divided clock output
      IOCLK				=> clk_in1p_bufio,	-- 1-bit output: I/O output clock
      SERDESSTROBE	=> clk_in1_strobe,	-- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
      I					=> clk1im_buf			-- 1-bit input: Clock input (connect to IBUFG)
   );

 

V2_input:

	clk1im_BUFIO2: BUFIO2 generic map (	-- buforuję zegar z wejścia, zeby taktować dane wejściowe. Przy okazji go odwracam
      DIVIDE			=> 7,				-- DIVCLK divider (1-8)
      DIVIDE_BYPASS	=> FALSE,		-- Bypass the divider circuitry (TRUE/FALSE)
      I_INVERT			=> FALSE,		-- Invert clock (TRUE/FALSE)
      USE_DOUBLER		=> FALSE--TRUE			-- Use doubler circuitry (TRUE/FALSE)
   )port map (
      DIVCLK			=> clk_in1_div,		-- 1-bit output: Divided clock output
      IOCLK				=> clk_in1p_bufio,	-- 1-bit output: I/O output clock
      SERDESSTROBE	=> clk_in1_strobe,	-- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
      I					=> clk1im_buf			-- 1-bit input: Clock input (connect to IBUFG)
   );

 

 Output for both versions:

   clk_in1_div_BUFG: BUFG port map (
      O => clk_in1_div_buf,			-- 1-bit output: Clock buffer output
      I => clk_in1_div					-- 1-bit input: Clock buffer input
   );


	not_clk_in1_div_buf	<=	not clk_in1_div_buf;

	d_scl_buf_ODDR2: ODDR2 generic map(
		DDR_ALIGNMENT	=> "NONE",		-- Sets output alignment to "NONE", "C0", "C1" 
		INIT				=> '0',			-- Sets initial state of the Q output to '0' or '1'
		SRTYPE			=> "SYNC"		-- Specifies "SYNC" or "ASYNC" set/reset
	)port map (
		Q	=> d_scl_buf,			-- 1-bit output data
		C0	=> clk_in1_div_buf,			-- 1-bit clock input
		C1	=> not_clk_in1_div_buf,		-- 1-bit clock input
		CE	=> '1',					-- 1-bit clock enable input
		D0	=> '1',					-- 1-bit data input (associated with C0)
		D1	=>	'0',					-- 1-bit data input (associated with C1)
		R	=> '0',					-- 1-bit reset input
		S	=> '0'					-- 1-bit set input
   );

 

I expected the first version to be 2x higher frequency due to use doubler => true.

I do not intend to output this clk, I just wanted to check what is wrong with my ISERDES. I get only every second 7b group.

 

Michał

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4 Replies
Highlighted
Instructor
Instructor
7,260 Views
Registered: ‎07-21-2009

Re: BUFIO2 use_doubler => true error ?

Michal,

 

It would save us all considerable time if you described how you expect your circuit (or your code) to work, and the results you are actually seeing.

 

Also, does logic simulation match your expected design results?

 

-- Bob Elkind

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Highlighted
Visitor
Visitor
7,255 Views
Registered: ‎09-06-2012

Re: BUFIO2 use_doubler => true error ?

If last 2 lines of the first post are not enough then below is much more detailed description.

 

clk1im_buf - is clock signal coming from ADC. It is DDR differential LVDS, It passes through IBUFGDS_DIFF_OUT, then goes into BUFIO2, and then into ISERDES2_clk0. There in second version clk1ip_buf that takes similar path, and then enters ISERDES2_clk1. In the beginning it is close to 100MHz, I am planning to increase it to the limits, that is 500MHz or 1GHz.

data1im_buf - data related to the clock is entering through IBUFDS, then IODELAY2 (for now in fixed mode), then ISERDES2_D.

Timing constrains related to the data1im_buf are met at ISERDES2.

 

In order to group the bits I use bitslip (I learned how to do it from your posts, you ware indicating that manual is inconsistent). Not in the way suggested in the literature, but I have written a module, that is triggered from the MCS, and that causes to step 1 bit at a time. I am able to get the pattern that ADC is sending, or rather halve of it. I am getting only 7b out of 14b that I want to get. Looking for errors, I decided to check the divclk coming out of BUFIO2. I expected it to be clk1im_buf/3.5, but what I saw is clk1im_buf/7. I made experiment with turning the doubler on and off. I saw no difference, I checked in the Google, checked in the forum. Is there something that prevents doubler from working?

 

I did not simulate the project. I still do not know how to make simulation when I have MCS. I will describe the signals, and if you tell that it is inevitable, I will remove most of the project and simulate only the vilat part.

 

Regards,

Michal

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Highlighted
Visitor
Visitor
7,214 Views
Registered: ‎09-06-2012

Re: BUFIO2 use_doubler => true error ?

I checked with different values of paramethers for BUFIO2. I never saw any influence of use_doubler true of false. I assume that it just does not work.

 

Michał

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Highlighted
Visitor
Visitor
6,444 Views
Registered: ‎06-06-2014

Re: BUFIO2 use_doubler => true error ?

Hi,

i was working with ISE 14.6 and also experienced that in the simulation USE_DOUBLER on a BUFIO2 works,

but on the hardware (xc6slx16-2csg324) it doesn't seem to have an effect, because the frequency of the clock at the output was half the frequency that i had expected.

so, yes, i can confirm that the USE_DOUBLER generic on a BUFIO2 (in VHDL, using ISE 14.6) on my Spartan6 is also not working. I just looked at my design in the FPGA Editor and couldn't find any USE_DOUBLER option. Perhaps it's not available on Spartan6??

Bertram

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