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Adventurer
Adventurer
8,211 Views
Registered: ‎03-30-2012

BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Hi:

 

I'm trying to use the solution in Answer Record #34276, which suggests using an unbonded IO as a routethrough to use its IDELAY element as a variable output delay.

 

I instantiated an IOBUF like this:

    (* LOC = "UNB48" *)
    IOBUF wrstrb_delay_iobuf(.I(wrstrb_from_ff),.O(wrstrb_to_delay),.T(1'b0),.IO(WRSTRB_DELAY));
and it happily went through synthesis and place-and-route, although it warned that it would create an "incorrect bitstream" ("Place:942 - An IO signal <IO> is constrained to an unbonded site <PAD48>. Processing will continue, but this will generate an incorrect bitstream. Please consider removing the IO constraint or constraining the IO to a bonded site.")

 

Bitgen absolutely refuses to generate a bitstream for this, even with the '-d' option which should turn off DRC:

 

bitgen -d iodelay_testing.ncd
Release 12.3 - Bitgen M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '6slx25.nph' in environment
C:\Xilinx\12.3\ISE_DS\ISE\.
   "iodelay_testing" is an NCD, version 3.2, device xc6slx25, package ftg256,
speed -3
Opened constraints file iodelay_testing.pcf.

Fri Mar 30 14:47:09 2012

Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ila_control<13> is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <vio/U0/I_VIO/reset_f_edge/iDOUT<1>> is
   incomplete. The signal does not drive any load pins in the design.
ERROR:PhysDesignRules:797 - Illegal placement. Component wrstrb_delay_iobuf/IO
   must be placed in a bonded site.
ERROR:Bitgen:25 - DRC detected 1 errors and 2 warnings.  Please see the
   previously displayed individual error or warning messages for more details.

 

Is there any way to actually do this any more, or is AR #34276 obsolete for some reason?

 

Thanks,

Patrick

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17 Replies
Scholar austin
Scholar
8,208 Views
Registered: ‎02-27-2008

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Patrick,


I would open a webcase.  Check that you have the right syntax to turn off the DRC.  It might be something simple:  turning off the DRC should always be possible.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Professor
Professor
8,204 Views
Registered: ‎08-14-2007

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Fri Mar 30 14:47:09 2012

Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ila_control<13> is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

 

It appears that you didn't actually turn off DRC.

 

-- Gabor

-- Gabor
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Adventurer
Adventurer
8,203 Views
Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

According to the BitGen docs adding "-d" turns off the DRC (or unchecking the Run Design Rules Checker (DRC) checkbox in ISE - I've tried both, neither works.

 

This problem was mentioned elsewhere on the forum, with no response:

 

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-unbonded-IO/m-p/210483

 

I would love to open a WebCase but I'm a University user. I can try to have a professor submit a webcase but I was hoping to have an answer sometime in the next month. :)

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Scholar austin
Scholar
8,197 Views
Registered: ‎02-27-2008

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

OK,


So, someone let me know if -d is right, and the tool is ignoring him, or if it should work, but the command is ????

 

And I will get it going.



Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
8,196 Views
Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Yes, I agree that it appears that DRC is still run, even with the -d option.

With the -d option, bitgen doesn't *produce* a DRC file (here iodelay_testing.drc is generated without -d, and if you delete it, running bitgen with -d won't regenerate it) but it apparently still runs DRC. Or at least does *something.*
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Adventurer
Adventurer
8,194 Views
Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Austin:

Well, I can tell you that the output from bitgen -help is:

Usage: bitgen [-d] [-j] [-b] [-w] [-l] [-m] [-t] [-n] [-u] [-a] [-r <bitFile>]
[-intstyle ise|xflow|silent|pa] [-ise <projectrepositoryfile>] {-bd
<BRAM_data_file> [tag <tagname>]} {-g <setting_value>} [-filter
<filter_file[.filter]>] <infile[.ncd]> [<outfile>] [<pcffile[.pcf]>]

Where:
-d = Don't Run DRC (Design Rules Checker)
(.. remainder snipped)

So at the very least, the tool's help is wrong. :)
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Scholar austin
Scholar
8,193 Views
Registered: ‎02-27-2008

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

It may run the DRC, but it should generate a .bit file with -d!



Austin Lesea
Principal Engineer
Xilinx San Jose
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Professor
Professor
8,183 Views
Registered: ‎08-14-2007

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

I don't have ISE 12.3, but at least in 12.4 I can turn on or off design rule checking

and see that it does make a difference.  I tried this with two projects, one Spartan 6

and another Spartan 3a DSP.  If this is a bug it seems pretty specific.  By the way,

I'm running under 32-bit Windows XP if that makes a difference.

 

-- Gabor

-- Gabor
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Adventurer
Adventurer
8,180 Views
Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

It actually makes a difference on any other NCD file I try as well - none of them say "Running DRC" with the -d option. Just this one.

Is there another option that needs to be set in the implementation processes maybe? It seems like there's something in the NCD that is telling BitGen it -has- to run DRC.
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Adventurer
Adventurer
6,420 Views
Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

It definitely doesn't generate the bitfile, that's for sure. :)

If you open the NCD in, for instance, the FPGA Editor, everything seems fine. If you unplace the nonbonded IOB (... making an incomplete design) then bitgen will generate a bitfile with '-d', and fail if you don't specify '-d' (because it's not fully routed).

But if there's an unbonded IO used in the design, it apparently always tries to run DRC, I guess.
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Adventurer
Adventurer
6,417 Views
Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Here's the NCD file if anyone wants to confirm what I'm saying. The device is a Spartan-6 LX25 - I haven't tried it with any other devices so it might be a Spartan-6 thing, but, well, that's what AR #34276 was talking about anyway. :)

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Scholar austin
Scholar
6,403 Views
Registered: ‎02-27-2008

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

All,

 

It seems the hardware isn't there on the unbonded pin (pin is unbonded in all packages, so driver isn't on the die).  DRC or no DRC, uou can't get a bitstream.

 

Austin

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
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Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Austin:

 

I don't understand - the UCF is constraining it to UNB48 (I've also tried UNB47, or using the PAD names PAD47/PAD48, same result in both). According to the pinlists, PAD47/PAD48 are bonded in the Spartan-6 LX25 FG484 package (pins A15/C15,  IO_L51N_0 and IO_L51P_0) and on the Spartan-6 LX25 CSG324 package (pins E12/F12).

 

Are the LX25 FG484/CSG324 package somehow a different die than the LX25 FTG256 (which... makes it odd that the device views in FPGA Editor, PlanAhead, etc. are identical)? If so are there *any* unbonded IOs that are usable on any of the Spartan-6s? If there are how do we tell which ones?

 

Patrick

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Scholar austin
Scholar
6,397 Views
Registered: ‎02-27-2008

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Patrick,


If it is bonded on some packages, then it is there in the layout.  All I can say is that it might be a bug, and you would need to file a webcase....

 

I did hear that sometimes bitgen will just not generate a bitstream if there is a design rule it just can't deal with (like missing hardware).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
6,395 Views
Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

Well, it's definitely bonded in all the other packages for this device, like I said, so this sounds like a bug. It sounds like I'll have to try to get a professor to open a WebCase on this.

 

It's annoying that BitGen doesn't give any information on why it's failing. Using an unbonded IO for it's IODELAY2 is a pretty useful trick, it's too bad that it doesn't seem to work due to software bugs.

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Adventurer
Adventurer
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Registered: ‎03-30-2012

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

I was just informed that apparently use of unbonded IOs is not possible on Spartan-6s, which is surprising in that it's not mentioned anywhere in documentation (whereas it was possible in previous generation chips).

 

So, yeah, AR#34276 is wrong. Too bad, because a variable-delay ODELAY without eating up a pin would be really nice.

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Visitor ustinforever
Visitor
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Registered: ‎03-02-2017

Re: BitGen won't allow unbonded IOs for routethrough (as in AR#34276) even with -d option

I found a way to use unbound IO in spartan-6 FPGA. 

 

I was using xc6slx9-tqg144. I wanted to use unbonded IO for IODELAY2, as AR #34276 suggest. I encountered exactly the same errors as peoples in this thread.

 

The solution was to change my pad names in my ucf file from something like P9 to something like PAD121(using "Package Pins" tab in PlanAhead I/O planning mode). I used unbounded IO for IODELAY2. After that i changed my package to biggest package available, csg324.

 

Looks like Impact do not check for actual FPGA package, so i was able to set all my pins correctly and use unbounded IO.

 

Hope it will help somebody who will come to this thread from Google in future, like me.

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