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Registered: ‎08-13-2012

Block RAM Instantiation Error

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Hello,

 

I'm trying to use Block RAM of 512x36 on Spartan3 device using ISE 14.1. I instantiated the X_RAMB16_S36_S36 in my design (verilog). I didn't include any verilog file for the RAM instantiation, hoping that the tool will take care of it. But when I started to synthesize the design to see if could infer a block ram, I got errors.

 

I'm getting

 

ERROR:HDLCompilers:244 - "../../Xilinx/14.1/ISE_DS/ISE/verilog/src/simprims/X_RAMB16_S36_S36.v" line 1878 'glbl.GSR' could not be resolved

ERROR:HDLCompilers:185 - "../../Xilinx/14.1/ISE_DS/ISE/verilog/src/simprims/X_RAMB16_S36_S36.v" line 1878 Illegal right hand side of continous assign

 

I then read about the GSR in Spartan User Manual. I understood that GSR can be used as global reset. Since my design is synchronous to one clock, I thought of using STARTUP_SPARTAN3 as mentioned in the documentation. I connected the system clock to CLK, GSR to system reset.

 

The errors disappeared, but new set of errors were generated.

 

Error:Xst - "../../Xilinx/14.1/ISE_DS/ISE/verilog/src/simprims/X_RAMB16_S36_S36.v" line 130: Unsupported tri0 net type.

Error:Xst:2228 0 "../../Xilinx/14.1/ISE_DS/ISE/verilog/src/simprims/X_RAMB16_S36_S36.v" line 1856: Unsupported Time variable.

 

I'm wondering why Xilinx synthesis is referring to this verilog file under simprims directory. I thought these files were behavioral files and have nothing to do with synthesis.

 

Can some please help me with the Block RAM instantiation?

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Registered: ‎08-13-2012
I figured out, the issue was with the instance X_RAMB16_S36_S36. The instance should be RAMB16_S36_S36. The X_RAMB16_S36_S36 is a behavioral model. Hence, ISE was throwing all these error when I tried to synthesize it.

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3,504 Views
Registered: ‎08-13-2012
I figured out, the issue was with the instance X_RAMB16_S36_S36. The instance should be RAMB16_S36_S36. The X_RAMB16_S36_S36 is a behavioral model. Hence, ISE was throwing all these error when I tried to synthesize it.

View solution in original post

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