cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor
Visitor
11,685 Views
Registered: ‎01-28-2010

CLOCK BUF routing error: Place 1136

Hello,

 

I get the error "ERROR:Place:1136 - This design contains a global buffer instance, <clk_int_BUFG>, driving the net, <clk_int_OBUF>, that is driving the following (first 30) non-clock source pins." I referred to http://www.xilinx.com/support/answers/33025.htm. But until the 'map' operation finishes, I cannot open FPGA editor (as sugested in the solution mentioned in the above link.

 

Kindly help out a newbie here.

 

Thanks.

Message Edited by ramanandn on 02-01-2010 11:04 AM
0 Kudos
7 Replies
Highlighted
9,523 Views
Registered: ‎05-19-2013

Re: CLOCK BUF routing error: Place 1136

Hello everyone ,

 

                          For me also getting error Place 1136 but not for clock signal,it is coming for Reset signal  the error is like this

 

Place:1136 - This design contains a global buffer instance,
<fpga_0_rst_1_sys_rst_pin1_BUFGP/BUFG>, driving the net,
<fpga_0_rst_1_sys_rst_pin1_BUFGP>, that is driving the following (first 30)
non-clock source pins.
< PIN: Inst_AD9361_SPI/c_s_FSM_FFd2-In.A3; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[5]_AND_68_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[6]_AND_66_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[14]_AND_50_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_spi_addr[13]_AND_20_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_wr_data_temp[3]_AND_88_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[7]_AND_64_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[13]_AND_52_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[8]_AND_62_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[12]_AND_54_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_spi_data[6]_AND_98_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[9]_AND_60_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_spi_data[1]_AND_108_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[2]_AND_74_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[11]_AND_56_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_wr_data_temp[4]_AND_86_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[0]_AND_78_o1.A2; >
< PIN: Inst_AD9361_SPI/spi_clk.SR; >
< PIN: Inst_AD9361_SPI/rst_spi_data[4]_AND_102_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_spi_data[7]_AND_96_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_addr_temp[1]_AND_76_o1.A2; >
< PIN: Inst_AD9361_SPI/rd_count_0.SR; >
< PIN: Inst_AD9361_SPI/rst_wr_data_temp[5]_AND_84_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_spi_addr[15]_AND_16_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_spi_data[2]_AND_106_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_spi_addr[14]_AND_18_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_wr_data_temp[6]_AND_82_o1.A2; >
< PIN: Inst_AD9361_SPI/rst_spi_addr[5]_AND_36_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_spi_data[5]_AND_100_o1.A4; >
< PIN: Inst_AD9361_SPI/rst_spi_addr[2]_AND_42_o1.A4; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "fpga_0_rst_1_sys_rst_pin1_BUFGP/BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
>

Phase 2.7 Design Feasibility Check (Checksum:45c342ec) REAL time: 48 secs

Total REAL time to Placer completion: 48 secs
Total CPU time to Placer completion: 48 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

    Please help me to solve this error 

 

Thanks&Regards

B.LAKSHMAN.

 

0 Kudos
Highlighted
Instructor
Instructor
9,518 Views
Registered: ‎07-21-2009

Re: CLOCK BUF routing error: Place 1136

Why are you using a BUFG clock buffer?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Community Manager
Community Manager
9,509 Views
Registered: ‎07-23-2012

Re: CLOCK BUF routing error: Place 1136

Hi Lakshman,

As clearly stated in the error message, you need to apply CLOCK_DEDICATED_ROUTE = FALSE; constraint on the reset net to convert this error into warning.

Regards,
Krishna
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
0 Kudos
Highlighted
Community Manager
Community Manager
9,508 Views
Registered: ‎07-23-2012

Re: CLOCK BUF routing error: Place 1136

Can you try opening *mapped.ncd file in standalone FPGA Editor tool?

If possible, refer to UG382 and lock the BUFG to upper part of the FPGA as mentioned in the article that you pointed out.
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
0 Kudos
Highlighted
Historian
Historian
9,506 Views
Registered: ‎02-25-2008

Re: CLOCK BUF routing error: Place 1136


@smarell wrote:
Hi Lakshman,

As clearly stated in the error message, you need to apply CLOCK_DEDICATED_ROUTE = FALSE; constraint on the reset net to convert this error into warning.

Regards,
Krishna

He needs to explain why he's got a BUFG on his reset signal.

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Community Manager
Community Manager
9,503 Views
Registered: ‎07-23-2012

Re: CLOCK BUF routing error: Place 1136

Probably, the reset net has high fan out.
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
0 Kudos
Highlighted
Historian
Historian
9,502 Views
Registered: ‎02-25-2008

Re: CLOCK BUF routing error: Place 1136


@smarell wrote:
Probably, the reset net has high fan out.

Yes, but ... the tools won't automatically insert a BUFG on a non-clock net. And if he instantiated it himself, then he knows what caused the error and he needs to remove the buffer.

 

If the reset is synchronous, the tools will replicate the reset signal enough to reduce the fanout such that he'll meet timing.

 

If the reset is asychronous, then he should change it to synchronous.

----------------------------Yes, I do this for a living.