04-09-2016 10:44 PM
I have my MPMC memory being made cachaeble address in microblaze.The DDR is connected to MPMC cntroller.When I want DDR memory being updated with values in cache, I flush it using microblaze_flush_dcache(). But the values are not updated. Any suggesion on this is welcome. Also I dont know which signals to debug in chipscope pro as source of microblaze_flush_dcache() is assembly code.Please also suggest on how can debug this.
Thanks in advance.
04-10-2016 03:28 AM
A cache flush will need to write the flushed data on the AXI data cache bus. You can probably put chipscope on that, and you should see traffic on your flush if you know for sure that you have unflushed data.
One thing to double check is if your microblaze is configured for write-back cache. If it is write-through the data will already be there.
04-10-2016 08:40 PM
Can someone post me a simple XPS project and SDK project with cache enabled and successfully flushed (more good if it comes with MPMC controller)
Thanks in advance