UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
924 Views
Registered: ‎03-08-2018

Can I use VREF pin for TMDS ?

Jump to solution

Dear All,

 

I'm trying to implement TMDS with spartan6lx16

 

But I confused that can I use VREF pin as TMDS in UCF ?

 

q112.JPG

 

 

Additionally,

 

When I use "VCCAUX = 3.3;" in UCF, Then I found the error message as the below

 

 

ERROR:Place:864 - Incompatible IOB's are locked to the same bank 2
Conflicting IO Standards are:
IO Standard 1: Name = LVCMOS33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR =
OUTPUT, DRIVE_STR = 12
List of locked IOB's:
DEBUG<0>
DEBUG<1>
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Would you help me what am I supposed to do to resolve this problem?

0 Kudos
1 Solution

Accepted Solutions
Community Manager
Community Manager
1,041 Views
Registered: ‎07-23-2015

Re: Can I use VREF pin for TMDS ?

Jump to solution

@love119 Your SYS_CLK and SW<0> nets are locked to the same pin A10. Check on this and modify. 

Also make sure the UCF matches to the board you are using since seems like you are reusing the same UCF from XAPP495 with modifications where needed.  

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
0 Kudos
5 Replies
Community Manager
Community Manager
904 Views
Registered: ‎07-23-2015

Re: Can I use VREF pin for TMDS ?

Jump to solution

@love119 


 But I confused that can I use VREF pin as TMDS in UCF ?

 


Yes you can if there is no VREF based IO Standard being used in that bank. From UG385

 

vref_s6.JPG

 


 When I use "VCCAUX = 3.3;" in UCF, Then I found the error message as the below

 Would you help me what am I supposed to do to resolve this problem?


Check this AR: https://www.xilinx.com/support/answers/39234.html 

What IO Standards do you have in bank 2? 

 

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
901 Views
Registered: ‎03-08-2018

Re: Can I use VREF pin for TMDS ?

Jump to solution

@gnarahar

 

I used 

LVCMOS33

in bank2.

 

 

Currently, Now I'm debugging with xapp495 example.

 

"xapp495 vtc demo" does not working.

 

Debug signals are connected in T9 and R9 in bank2

 

###########################################
# Setting VCCAUX for different SPARTAN6LX16 2FT256 board
###########################################
#VCCAUX = 3.3;

########################################
# Reset button and LEDs
########################################
NET "RSTBTN"        LOC = "T8";
#NET "LED<0>"        LOC = "H12";
#NET "LED<1>"        LOC = "G13";
#NET "LED<2>"        LOC = "E16";
#NET "LED<3>"        LOC = "E18";

##############################################################################
# SYSCLK Input
##############################################################################

NET "SYS_CLK"       LOC = A10 	| IOSTANDARD = LVTTL;

##############################################################################
# Mechanical Switches (SW)
##############################################################################

#NET "SW<0>"         LOC = "A10" | IOSTANDARD = LVCMOS33 ;
#NET "SW<1>"         LOC = "D14" | IOSTANDARD = LVCMOS33 ;
#NET "SW<2>"         LOC = "C14" | IOSTANDARD = LVCMOS33 ;
#NET "SW<3>"         LOC = "P15" | IOSTANDARD = LVCMOS33 ;


##############################################################################
# Debug Port # JA1
##############################################################################
NET "DEBUG[1]" LOC = T9 | IOSTANDARD = LVCMOS33;
NET "DEBUG[0]" LOC = R9 | IOSTANDARD = LVCMOS33;

##############################################################################
# DCM/PLL/BUFPLL positions
##############################################################################
#INST "PCLK_GEN_INST" LOC = "DCM_X0Y3"; 
#INST "PLL_OSERDES"   LOC = "PLL_ADV_X0Y1";
#INST "ioclk_buf"     LOC = "BUFPLL_X1Y0";

###########################################
# Timing Constraints
###########################################
NET "clk50m_bufg" TNM_NET = "TNM_CLK50M";
TIMESPEC "TS_CLK50M" = PERIOD "TNM_CLK50M" 50 MHz HIGH 50 % PRIORITY 0 ;

NET "pclk" TNM_NET = "TNM_PCLK";
TIMESPEC "TS_PCLK" = PERIOD "TNM_PCLK" 108 MHz HIGH 50 % PRIORITY 0 ;

NET "pclkx2" TNM_NET = "TNM_PCLKX2";
TIMESPEC "TS_PCLKX2" = PERIOD "TNM_PCLKX2" TS_PCLK * 2;

NET "pclkx10" TNM_NET = "TNM_PCLKX10";
TIMESPEC "TS_PCLKX10" = PERIOD "TNM_PCLKX10" TS_PCLK * 10;

#
# Multi-cycle paths
#
#TIMEGRP "bramgrp" = RAMS(enc0/pixel2x/dataint<*>);  
#TIMEGRP "fddbgrp" = FFS(enc0/pixel2x/db<*>);
#TIMEGRP "bramra" = FFS(enc0/pixel2x/ra<*>);

#TIMESPEC "TS_ramdo" = FROM "bramgrp" TO "fddbgrp" TS_PCLK;
#TIMESPEC "TS_ramra" = FROM "bramra" TO "fddbgrp" TS_PCLK;

############################
# TMDS pairs on the top
############################
#NET "TMDS(0)"  	LOC = "C7" | IOSTANDARD = TMDS_33 ; # Blue
#NET "TMDSB(0)"  LOC = "A7" | IOSTANDARD = TMDS_33 ;
#NET "TMDS(1)"  	LOC = "D8" | IOSTANDARD = TMDS_33 ; # Red
#NET "TMDSB(1)"  LOC = "C8" | IOSTANDARD = TMDS_33 ;
#NET "TMDS(2)"  	LOC = "B6" | IOSTANDARD = TMDS_33 ; # Green
#NET "TMDSB(2)"  LOC = "A6" | IOSTANDARD = TMDS_33 ;
#NET "TMDS(3)"  	LOC = "B8" | IOSTANDARD = TMDS_33 ; # Clock
#NET "TMDSB(3)"  LOC = "A8" | IOSTANDARD = TMDS_33 ;


NET "TMDS[0]"  	LOC = "F9"    | IOSTANDARD = TMDS_33 | DRIVE = 8  | SLEW = FAST;# Blue
NET "TMDSB[0]"  	LOC = "D9"    | IOSTANDARD = TMDS_33 | DRIVE = 8  | SLEW = FAST;
NET "TMDS[1]"  	LOC = "F10"   | IOSTANDARD = TMDS_33 | DRIVE = 8  | SLEW = FAST;# Red
NET "TMDSB[1]"  	LOC = "E11"   | IOSTANDARD = TMDS_33 | DRIVE = 8  | SLEW = FAST;
NET "TMDS[2]"  	LOC = "E10"   | IOSTANDARD = TMDS_33 | DRIVE = 8  | SLEW = FAST; # Green
NET "TMDSB[2]"  	LOC = "C10"   | IOSTANDARD = TMDS_33 | DRIVE = 8  | SLEW = FAST;
NET "TMDS[3]" 		LOC = "D8"    | IOSTANDARD = TMDS_33 | DRIVE = 8  | SLEW = FAST;# Clock
NET "TMDSB[3]" 	LOC = "C8"    | IOSTANDARD = TMDS_33 | DRIVE = 8  | SLEW = FAST;







##############################################################################

 

Then what am I supposed to do to resolve this problem?

Should I remove  

VCCAUX = 3.3;

0 Kudos
Community Manager
Community Manager
1,042 Views
Registered: ‎07-23-2015

Re: Can I use VREF pin for TMDS ?

Jump to solution

@love119 Your SYS_CLK and SW<0> nets are locked to the same pin A10. Check on this and modify. 

Also make sure the UCF matches to the board you are using since seems like you are reusing the same UCF from XAPP495 with modifications where needed.  

 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
871 Views
Registered: ‎03-08-2018

Re: Can I use VREF pin for TMDS ?

Jump to solution

@gnarahar

 

#NET "SW<0>"         LOC = "A10" | IOSTANDARD = LVCMOS33 ;

 

SW<0> has already commented, is this wrong?

0 Kudos
Explorer
Explorer
861 Views
Registered: ‎03-08-2018

Re: Can I use VREF pin for TMDS ?

Jump to solution

@gnarahar

 

Would you let me know timing constraints, when the input clock is set as 50Mhz.

Currently I used the below UCF But I'm confused 108Mhz how to work in 50Mhz input clock.

 

Can I use these constraints for implement at 50mhz input clock ?

 

NET "clk50m_bufg" TNM_NET = "TNM_CLK50M";
TIMESPEC "TS_CLK50M" = PERIOD "TNM_CLK50M" 50 MHz HIGH 50 % PRIORITY 0 ;

NET "pclk" TNM_NET = "TNM_PCLK";
TIMESPEC "TS_PCLK" = PERIOD "TNM_PCLK" 108 MHz HIGH 50 % PRIORITY 0 ;

NET "pclkx2" TNM_NET = "TNM_PCLKX2";
TIMESPEC "TS_PCLKX2" = PERIOD "TNM_PCLKX2" TS_PCLK * 2;

NET "pclkx10" TNM_NET = "TNM_PCLKX10";
TIMESPEC "TS_PCLKX10" = PERIOD "TNM_PCLKX10" TS_PCLK * 10;
0 Kudos