I have been trying without success to initiate a reconfig via ICAP and want to double check some of my assumptions based off of what I've read from the UG380 doc.
The first is, in case of failure, where there is not a valid PROM image (golden or multiboot) on the attached flash, is the FPGA supposed to basically be a blank slate without any logic on it? Or will it continue to run whatever bitstream is already programmed to it.
Second, a clarification on the format the PROM image is itself supposed to take. On page 128 of UG380 we have a diagram that shows a header located at address 0. I assume this header is distinct from say an actual bitstream that contains the logic we want to program the FPGA with?
The other thing I'd like to get a clarification on is the address used for the GENERAL_1/2 registers. They are for the multi-boot start address. When I generate a bin file for the flash, it has a "header" section that is 16 bytes of FF and then four bytes, AA 99 55 66. Is the multi-boot start address supposed to be set to where those 16 bytes of FF or someplace after?
1) Since you have to give a IPROG command before the ICAP configuration, the FPGA will be not program with the original bitstream if both the multiboot and the fallback fail. However it is not completely blank.
The Internal PROGRAM (IPROG) command is a subset of the functionality of pulsing the PROGRAM_B pin. The fundamental difference is that the IPROG command does not erase the WBSTAR, TIMER, and other internal registers used during MultiBoot and fallback. The IPROG command triggers an initialization, and both INIT and DONE go Low when the IPROG command is issued followed by an attempt to configure.
PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.