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leop.pelletier
Observer
Observer
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Registered: ‎04-05-2011

Clock Routing error on Spartan 6 - X150

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Hello,

 

Due to a series of errors in the design stage of a prototype board, the only differential clock traces to our Spartan-6 XC6SLX150 ended up connected to D8 and D9 multifunction pins (IO_L64P_D8_2 and IO_L64N_D9_2).  Is it still possible to route a clock signal through these pins to the PLL? Would there be undesirable consequences? What is the maximum frequency that can be applied to a non-clock input?

 

I tried looking in the various datasheets for information, but I am not very familiar with the Xilinx FPGAs yet and got somewhat lost in the different terminologies. Please forgive me if the answer is obvious, but I'd really like to avoid mcGyvering a solution to have the clock signal available on a GCLK pin.

 

Thank you very much for your help!

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austin
Scholar
Scholar
3,581 Views
Registered: ‎02-27-2008

l,

 

It appears that the pins you have are a differential pair (P and N inputs capable) so that is very good.  No pin is any different from any other insofar as the IOB circuitry goes:  any pin is as fast, and as "good" as any other pin (or pair of pins).  The dedicated clock pins have one special attribute:  their delay is guaranteed (the delay to get to the global clock resources) and can be manged by the tools to meet timing for IO constraints (before and after timing constraints).  When you use a non-global IO pin, you lose the ability to get guaranteed closure for the timing of IO signals.  But, you may have so much slack (margin) that it will not be a problem, or the timing mnay be able to be adjusted (useing the phase shift feature of the DCM).

 

Observing the delays in trace (or in FPGA Editor) will give you some idea of what the worst case, maximum delay is, and the best case delay might be three, or even four times smaller than the worst case.

 

Frequency of operation is no issue, as is termination and impedance matching (same as any other pair of pins).

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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austin
Scholar
Scholar
3,582 Views
Registered: ‎02-27-2008

l,

 

It appears that the pins you have are a differential pair (P and N inputs capable) so that is very good.  No pin is any different from any other insofar as the IOB circuitry goes:  any pin is as fast, and as "good" as any other pin (or pair of pins).  The dedicated clock pins have one special attribute:  their delay is guaranteed (the delay to get to the global clock resources) and can be manged by the tools to meet timing for IO constraints (before and after timing constraints).  When you use a non-global IO pin, you lose the ability to get guaranteed closure for the timing of IO signals.  But, you may have so much slack (margin) that it will not be a problem, or the timing mnay be able to be adjusted (useing the phase shift feature of the DCM).

 

Observing the delays in trace (or in FPGA Editor) will give you some idea of what the worst case, maximum delay is, and the best case delay might be three, or even four times smaller than the worst case.

 

Frequency of operation is no issue, as is termination and impedance matching (same as any other pair of pins).

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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leop.pelletier
Observer
Observer
2,885 Views
Registered: ‎04-05-2011

That's great, I will give this a try!

 

Thank you very much :)

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