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Visitor
Visitor
4,055 Views
Registered: ‎07-30-2013

Clock options for video input

Hi

 

I am building an FPGA circuit that will accept a parallel 16bit raw digital video input and serialize to an LVDS input for a flat panel screen. The pixel rate is 40Mhz and the LVDS is 280MHz, serializes is a t a rate of 1:7.  I can think of 2 clocking options but i'm unsure which will be best.

 

1 . The clock is taken from the pixel clock at 40Mhz, an internal DCM multiplies this by 7 to produce 280Mhz, the logic all runs at this speed.

 

2. To use an external clock of 28Mhz, use a DCM  x10 to create 280Mhz, the video input is then over sampled to determine the data transitions.

 

So i guess what i'm trying to say is, would it best to use the pixel clock clock to drive the circuit or use an external clock and over sample the video input.

 

Any help would be appreciated, thanks.

 

Steve

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Instructor
Instructor
4,036 Views
Registered: ‎07-21-2009

What device family and speed grade are you using?

 

Suggest you run all of your logic with the 40MHz pixel clock, and serialise to 280MHz (x7) with clock generated by DCM or PLL.  If Spartan-6, use OSERDES2.  If Spartan-3, you may need to use a FIFO to bridge the two clock domains.

 

-- Bob Elkind

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Visitor
Visitor
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Registered: ‎07-30-2013

Hi Bob

 

Thanks for the speedy reply.  

 

I am using a Spartan 6 part so i'll look into the OSERDES2 primitive.  

 

I also need to run some logic which creates a splash-screen when no video input is detected.  When the pixel video clock is detected the splash screen disables and the video is serialized and output.

 

Would it be sensible to run this splashscreen and drive the LVDS logic with an external clock while continuously sampling the video pixel clock for activity, then switch to the video when the pixel clock is detected switch the outputs?

 

 

Steve

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Instructor
Instructor
4,032 Views
Registered: ‎07-21-2009

Would it be sensible to run this splashscreen and drive the LVDS logic with an external clock while continuously sampling the video pixel clock for activity, then switch to the video when the pixel clock is detected switch the outputs?

 

If the input video pixel clock is not a constant clock source, then you clearly must provide an alternative clock.  There are several design approaches which can work for the application you describe -- just pick one and forge ahead.

 

Personally, I would not switch clock sources.  I would provide a constant, fixed timebase for internal logic, and design a path for bridging the input video signal to the internal timebase.  Typical implementations use either oversampling (and input pixel clock edge detection) or FIFOs.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Professor
Professor
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Registered: ‎08-14-2007

My favorite approach for a constant internal clock is to use a frequency that's slightly higher than the maximum input pixel clock rate.  Then use a short FIFO (it will be normally almost empty) between the input clock and the constant clock.  Since the constant clock is slightly faster, if you always enable both write and read on the FIFO you won't ever overflow and you can use the not EMPTY condition as a clock enable or data valid signal downstream of the FIFO.  If your external video source can go away, you'll probably need to reset the FIFO when you detect the video coming in afterwards.  That can help if the FIFO becomes "confused" due to clock glitches when the external source starts up.

 

I generally frown upon using oversampling with an unrelated clock if there is a clock available from the video source itself.  It's also possible to use the FIFO's EMPTY output to detect the incoming clock frequency.  Counting non-empty cycles over some reasonably large time period can give you a reasonable accurate reading.  Note that a stopped input clock can prevent flags from propagating through a FIFO, but the EMPTY flag is "conservative" meaning that if the FIFO could be empty the flag will be asserted as long as you continue to provide the read clock.  Thus you can also detect lack of input using the EMPTY cycle count (frequency less than some threshold).

-- Gabor