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Adventurer
Adventurer
7,774 Views
Registered: ‎07-06-2010

Clock routing to BUFGMUX

Hi,

I am using spartan3 xc3s5000 in my design. How can I stop xilinx ISE from routing my clock to BUFGMUX? what's happening is that when I instantiate a core of chipscope in my design, xilinx routes the clock to BUFGMUX. The clock is a direct output of DCM and the clock is also driving other modules.

 Also, xilinx routes my two other internal signals to BUFGMUX as well. How can I tell xilinx not to do it and route the signals using local routing?

 

Here's my clock report:

 

Clock Net Routed Resource Locked Fanout Net Skew(ns) Max Delay(ns)
mclk_50mhz ROUTED BUFGMUX3 No 4537 0.883000 1.741000
last_round_done_1 ROUTED BUFGMUX7 No 205 0.681000 1.581000
last_round_done_2 ROUTED BUFGMUX2 No 181 0.551000 1.501000
control0<0> ROUTED BUFGMUX6 No 144 0.636000 1.498000
d_clk2_IBUF ROUTED BUFGMUX4 No 2 0.032000 1.529000
d_clk1_IBUF ROUTED BUFGMUX5 No 2 0.119000 1.529000
e_clk1_IBUF ROUTED BUFGMUX1 No 2 0.109000 1.529000
e_clk2_IBUF ROUTED BUFGMUX0 No 2 0.103000 1.502000
rcvd_replica1 ROUTED Local   1186 0.000000 9.462000
control0<13> ROUTED Local   5 0.000000 0.397000
icon/U0/iUPDATE_OUT ROUTED Local   1 0.000000 4.114000
clk_posedge_pulse_prolonged_delay ROUTED Local   1 0.000000 1.026000
clk_posedge_pulse_prolonged_delay ROUTED Local   1 0.000000 1.696000
clk_posedge_pulse_prolonged_delay ROUTED Local   1 0.000000 1.135000
clk_posedge_pulse_prolonged_delay ROUTED Local   1 0.000000 1.226000

 

 

As you can see in this report control0<0> is routed to BUFGMUX6, also my two internal signals last_round_done1 & 2, I want to use these resources for other purposes but this thing is not allowing me to do so.

 

Regards

-- Hassan --

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7 Replies
Teacher eteam00
Teacher
7,765 Views
Registered: ‎07-21-2009

Re: Clock routing to BUFGMUX

what's happening is that when I instantiate a core of chipscope in my design, xilinx routes the clock to BUFGMUX. The clock is a direct output of DCM and the clock is also driving other modules.

 

A BUFGMUX is a global clock buffer.  When it is being used as a simple clock buffer -- instead of being used as a clock mux + buffer -- it is usually called (simply) BUFG.

 

The global clock buffer ensures that clock skew is essentially zero across the enture FPGA.  If a clock is distributed in "local routing", clock skews are almost guaranteed to cause even a very small design to fail.  Remember, skew will cause design failure at ANY clock frequency.

 

Is XST  buffering non-clock signals with clock distribution buffers?  If so, this is unusual.  Would you be willing to post your code for a quick second-opinon type check?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Adventurer
Adventurer
7,749 Views
Registered: ‎07-06-2010

Re: Clock routing to BUFGMUX

here's the code snippet , the reported signal is in encryption core and decryption core.

 

the signals last_round_done1 in clock report refers to the aes_last_round_done_key2 in encryption core and

the signals last_round_done2 refers to the aes_last_round_done_key2 in decryption core

 

always @(posedge mclk or posedge reset)
        if (reset)     aes_last_round_done_key2 <= 1'b0;
        else            aes_last_round_done_key2 <= aes_last_round_done;

 

assign aes_last_round_done =   (aes_round == 4'hb) &&
                                                             msm_start_9th_AES_round;

 

 

1- aes_round is a counter counting on the basis of state machine.

2- msm_start_9th_AES_round is the signal generated on the basis of state machine.

 

I don't know if this code will be of any help, I don't see any point of XST routing it to BUFGMUX.

 

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Adventurer
Adventurer
7,747 Views
Registered: ‎07-06-2010

Re: Clock routing to BUFGMUX

Also, regarding the chipscope instantiation thing, the mclk_50Mhz signal in the clock report is the output of my DCM. Here's how we have floorplanned the signals:
mclk -> GCLK
mclk goes to DCM.
mclk_50Mhz is the output of DCM, so it is going to a BUFGMUX, that i understand.
mclk_50Mhz is used in the entire FPGA, and it is already buffered, then why would it rebuf the signal for chipscope core only? Am I missing something here ?
Because when I comment the chipscope core and then run P&R, the clock report doesn't show control0<0> in the clock report so my BUFGMUX is available for use.

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Visitor fengliu
Visitor
7,548 Views
Registered: ‎08-23-2012

Re: Clock routing to BUFGMUX

Hi,

I have the same issue that XST route the non clock signal to BUFGMUX. Is there any answer or solution yet?

Thanks,

Feng

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Teacher eteam00
Teacher
7,546 Views
Registered: ‎07-21-2009

Please start a new thread

fengliu,

 

please start a new thread.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Highlighted
Visitor fengliu
Visitor
7,544 Views
Registered: ‎08-23-2012

Re: Please start a new thread

Hi Bob,
How to start a new thread?
Thanks,
Feng
Tags (1)
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Teacher eteam00
Teacher
7,538 Views
Registered: ‎07-21-2009

Re: Please start a new thread

How to start a new thread?

 

Navigate to the forum in which you want to post your thread.  Then click on the "new message" button.

 

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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