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Registered: ‎07-15-2010

Clocking regions in XC6SLX25-FTG256



our current design was developed for a XC6SLX16-FTG256 device and was planed to be implemented later in a XC6SLX25-FTG256 device. In an older version of UG385 (v1.2) from February 2010, both devices should be absolutely pin compatible. According to the current UG385 (v2.2) the pinouts of XC6SLX16 and XC6SLX25 are different.


The design fits and works in a SLX16 device.


Now in the SLX25 device GCLK8…GCLK11 are shifted from the RT region to the RB region,

GCLK20…GCLK23 are shifted from the LT region to the LB region. Therefore in the regions RB and LB there are 8 GCLK inputs, in the regions RT and LT there are not any GCLK inputs available.


In our design, LVDS lines were placed in the RT region and shall be driven by a clock from GCLK10 (J12) and GCLK11 (J11), which are now in SLX25 device in the RB region.


According to UG382 page 22, “it is possible to span an entire bank with a single global clock input that is connected to two BUFIO2 buffers in different BUFIO2 clocking regions to span an entire edge of the device”, asumed IODELAY2 are not used.

Applying this, the design seems to be unroutable. The mapper locates the IO  BUFIO2s  to improper regions resulting in unroutable design.


Each trials to allocate the BUFIO2s by LOC constraints caused conflicts.


How to find out which IO components (BUFIO2s, IODELAY2s, ISERDES) are related to the selected GCLK pins for XC6SLX25-FTG256 device?


In the attached file there are pin locations of the applied LVDS busses. 


Thanks in advance 


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2 Replies
Registered: ‎07-15-2010

In the additional attached file there is an example of locking the BUFIO2s

and the reported errors.



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Registered: ‎07-15-2010

Problem solved now: 


There is a clock which needs to drive IO components located in two clock regions RT and RB.
This clock was connected to two BUFIO2_2CLK buffers in different BUFIO2 clocking regions to span an entire edge of the device.
Both BUFIO2_2CLKs provide a clock for the IO components in the proper region.
Only one of the BUFIO2_2CLKs provides a DIVCLK_fbus as global clock for the entire design.
DIVCLK_fbus output must be connected to a proper BUFGMUX.

DIVCLK_fbus was provided by the BUFIO2_2CLK from RB region, which has to be connected to BUFGMUX_X2Y4.
Exactly the same BUFGMUX is occupied by DIVCLK_adc from BUFIO2_2CLK from TR region where the ADC bus is located.

In order to force a proper access from BUFIO2_2CLK to a free BUFGMUX, the mapper put the BUFIO2_2CLKs
by itself to a wrong region and reported this later as an user action:

*ERROR:Place:1171 - The BUFIO instance   <user_logic_i/fbus/FBUS_serin/clk_gen/BUFIO_fbus_n> needs to have all of its
IOB loads placed into its same half IO bank. However, **the user has locked it ** to site <BUFIO2_X4Y21>,
and locked its IOB load <f0_p> to site <PAD91>, which is in a different half IO bank.
Please check user-specified LOCATION constraints and make sure they do not violate this rule.*

In this run not any LOC constraints for BUFIO2s were done, therefore the error report is confusing.

The problem is solved when DIVCLK_fbus is provided by the other BUFIO2_2CLK from RT region,
which has to be connected to BUFGMUX_X2Y1.
In this way, BUFGMUX_X2Y4 is available for DIVCLK_adc from BUFIO2_2CLK from TR region of the ADC bus.