01-05-2015 05:41 AM
Dear Xilinx community,
As I promised while ago, if I find way to convert Analog signal to Digital using VHDL on Spartan I would publish my work here for users.
Not only I publish it here, but I am going to revelal how I realized Lock-in amplifier on Spartan 3E FPGA board and used LCD display on board to show all necessary data.
I ask you to check my source and include it in basic tutorials if code is reliable. I am not genius guy, I like very straightforward things. So I believe it could help beginners.
01-05-2015 05:50 AM
I am attaching my Master Thesis, which received 70% mark, and VHDL source code with averaging and exponential filters.
This work is combination of different examples and methods I found on the Internet.
I advice you try to run it first. But at the end not only copy and paste, but try to understand all parts, since it needs time to fully recover it.
Analog way of realization is also included.
04-06-2015 08:07 AM
Thank you very much for your contribution !! I was just needing how to implement a lock-in amplifier in FPGA and I came across your contribution. Could you upload, please, the code for the Test Bench?
Thank you very much!! and I'll be waiting for you answer.
04-19-2015 02:36 AM
06-04-2015 08:47 AM
Thanks so much for posting this!
I tried compiling this using the ISE Design Suite 14.7 (with free WebPack license); however, I got the following error:
ERROR:HDLParsers:3014 - "C:/Users/.../Lock_in/REF_FREQUENCY.vhd" Line 23. Library unit funct is not available in library work.
I'm a student just learning how to use this software so any help is greatly appreciated!
07-22-2015 02:50 PM
07-23-2015 09:25 PM
07-20-2016 03:21 AM
I am using the code you have uploaded here to realize lock in amplifier. The code is working with your testbench. I was using example.vhd as testbench . But when I try to implement it with a slightly different set of values for same sine wave , I dont get any result properly. Any suggestions on this issue.
Your sine values: (200,202,204,206,208,210,211,213, --scale to 4194304
My sine values: 200,202,204,206,208,210,211,213,
Please suggest a solution as soon as possible.
07-25-2016 03:31 AM
Did you read doc file? It is hard to remember after 2 years. But it worked with real signals with introduced noise. There is sinewave generator inside logic. And use averaging filter. It is much simplier...
07-31-2016 10:32 PM
I was able to give sine values from LUT and get correct output after making a clock crossing circuit of 2 FF synchronizer in REF_FREQUENCY.vhd for ref_period_int for crossing from spartan clock to clk_in. But when I give real time sine values from ADC and probe at the Zero crossing detector out , it is Ok. At the same time if I probe the REF_FREQUENCY ,vhd 's DDS_feedback_out it is not correct value jumps abruptly from one value to other. Note it , I have not changed any components heirachically from lock_in_amp.vhd for interfacing to ADC. Still this error occurs. I am struggling with this for 2 weeks. Please help.
Attached is my project.
As far as I understood in REF_FREQUENCY.vhd if reference_sync_wave,SPARTAN_clk,clk_in is correct then DDS_feedback_out should be correct ..Right?
08-03-2016 04:20 AM
08-03-2016 04:45 AM
Any idea how to get back original sine wave from noise using I and Q out from lock in amplifier and DAC? That is how to use I and Q outputs from lock in amplifier to reconstruct original sine wave of frequency?
08-04-2016 02:25 AM
Can't we measure phase of signal with respect to reference from the I and Q outputs of lock in amplifier from this design?
i understood we can measure the amplitude of the signal taking root of squared sum of I and Q values. please reply.
02-22-2017 01:53 AM
Thanks for your uploaded code. I tested the code with actual hardware but which gave perfect I and Q values. But when I introduced noise in the signal it was not able to detect the signal.
Can you please look into the matter and tell if you have uploaded the latest code or not?
03-13-2017 09:20 PM
03-13-2017 09:24 PM
I am not using any evaluation board. I am using saturn spartan6 board from numato and my ADC is TI ADS1278 evaluation board.
01-24-2018 12:48 AM
Thank you so much for your code. I am a student. I read your master thesis. I tried to run your code on spartan 3E FPGA. But LCD only shows the 0 value as out put. I give V reference = 0.525V, offeset= 1.64V with 1000Hz frequency. and signal is 1.255V, offeset= 1.64V with 1000Hz frequency. But it's not giving output as you showed in your thesis.
I simulate all modules individually and they works. I am not getting where the problem is. Can you help me in this?
even I cannot simulate whole LIA with your given testbench in forum as per your thesis.
Please help me.
02-09-2018 06:28 AM - edited 02-20-2018 02:42 AM
I am a student too,and I want to learn to use FPGA, but also to use Spartan 3e. However I can not download or open the file EEE2014-MSc.docx
If you can see his master's thesis, can you send me a copy, so that we can learn together and exchange
Thank you very much!
02-20-2018 01:24 AM