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Visitor benkhoff
Visitor
12,712 Views
Registered: ‎02-23-2016

Comunication to DDR3 RAM using MIG

process (c1_clk0)
begin
	if(rising_edge(c1_clk0)) then
		
		case ram_state is
		when	ready =>
				led(2) <= '1';
				LED(3) <= '1';
				
			if(c1_calib_done = '1') then
				-- init NULL
				c1_p0_cmd_en <= '0';
				c1_p0_cmd_instr <= "000";
				c1_p0_cmd_bl <= "000000";
				c1_p0_cmd_byte_addr <= (others => '0');--"000000000000000000000100000000";--(9 => '1', others => '0'); Start_addr -2
				c1_p0_wr_en <= '0';
				c1_p0_wr_mask <= "0000";
				c1_p0_wr_data <= (others => '0');
				c1_p0_rd_en <= '0';
				ram_state <= write_ram;
			end if;
			
		
		when write_ram =>
				led(2) <= '0';
				LED(3) <= '1';
			if(c1_p0_wr_full = '0') then
				led(2) <= '0';
				LED(3) <= '0';
					if(wait_cnt < 2) then
						wait_cnt <= wait_cnt + 1;
						c1_p0_wr_en <= '0';
						c1_p0_wr_mask <= "0000";
						c1_p0_wr_data <= count;
						wr_cnt <= c1_p0_wr_count;
					elsif(wait_cnt < 3) then
						wait_cnt <= wait_cnt + 1;
						c1_p0_wr_en <= '1';
					else
						wait_cnt <= 0;
						ram_state <= wr_end;
					end if;

			end if;

		when 	wr_end =>
			led(2) <= '0';
			count <= count + 1;
			c1_p0_wr_en <= '0';
			c1_p0_cmd_en <= '0';
			ram_state <= write_command;
			when	write_command =>
			led(2) <= '1';
			led(3) <= c1_p0_cmd_full;
			if(count < 16) then
				count <= count + 1;
			if(c1_p0_cmd_full = '0') then
				led <= "0000";
				if(wait_cnt < 2) then
					c1_p0_cmd_en <= '0';
					c1_p0_cmd_instr <= "000";
					c1_p0_cmd_bl <= "000001";
					c1_p0_cmd_byte_addr <= "000000000000000000000100000000";
					wait_cnt <= wait_cnt + 1;
				elsif(wait_cnt = 2) then
					c1_p0_cmd_en <= '1';
					wait_cnt <= wait_cnt + 1;
				elsif(wait_cnt = 3) then
					wait_cnt <= 0;
					c1_p0_cmd_en <= '0';
					ram_state <= read_ram;
				end if;
			end if;
			end if;
		when	read_ram =>
			led(3) <= '1';
			c1_p0_cmd_en <= '1';
			c1_p0_cmd_instr <= "001";
			c1_p0_cmd_bl <= "000100";
			c1_p0_cmd_byte_addr <= rd_addr;
			rd_addr <= rd_addr + 1;
			rd_set <= '1';
			if((ftdi_ready = '1') and (c1_p0_rd_empty = '1') and (rd_set = '1')) then
				ftdi_send <= '1';
				c1_p0_rd_en <= '1';
				rd_data <= c1_p0_rd_data(7 downto 0);
				rd_set <= '0';
				ram_state <= st_wait;
			end if;
			when read_end =>
				ram_state <= st_wait;
		when	st_wait =>
			c1_p0_cmd_en <= '0';
			ftdi_send <= '0';
			c1_p0_rd_en <= '0';
			ram_state <= ready;
		end case;
	end if;

end process;

Hello,

we are using a Spartan6 LX75 Development Board T0630 (http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE0630_series/TE0630/documents/UM-TE0630.pdf

On this Board there is the DDR3 RAM from Nanya (NT5CB64M16DP). For programming we use VHDL and ISE 14.7

We created a RAM interface using MIG.

Now there are problems with the communication. I have build a state machine using the ug388 (see code).

i have the problem the calib_done pin never turns high level

 

do you maybe have an idea what to change or a code example comunicating to a interface generated by the MIG

Thanks

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5 Replies
Xilinx Employee
Xilinx Employee
12,698 Views
Registered: ‎07-11-2011

Re: Comunication to DDR3 RAM using MIG

@benkhoff

Calib_done is zero in simulation or in hardware?

Please use example design as-is and check if calibration passes, then you can add your own user interface logic.

 

You can refer UG416 for the details 

http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_8/ug416.pdf

 

Hope this helps

 

-Vanitha

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Visitor benkhoff
Visitor
12,694 Views
Registered: ‎02-23-2016

Re: Comunication to DDR3 RAM using MIG

calib_done stays low in hardware.

 

i have used the simuation of the example design and there calib_done goes low after about 26 us.

thanks for the link to the user guide, i have read this but still got questions on how to exactly speak to the generated interface.

 

in general the procedure is

1. write data to write fifo (at least 32 bits)

2. write "write" command "000" to command fifo

3. write "read" command

4. read data from read fifo

is this correct?

 

sorry for the basic questions i have never used an external memory with a fpga.

 

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Visitor benkhoff
Visitor
12,690 Views
Registered: ‎02-23-2016

Re: Comunication to DDR3 RAM using MIG


@benkhoff wrote:

i have used the simuation of the example design and there calib_done goes low after about 26 us.


sorry for the mistake the calib_done signal goes to high level after 26 us

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Xilinx Employee
Xilinx Employee
12,689 Views
Registered: ‎07-11-2011

Re: Comunication to DDR3 RAM using MIG

@benkhoff

 

Your user interface FSM should not have any effect on calibration, write/read comamnds come into picture only after calibration.

I would suggest you to go through below XIlinx AR and follow the given debug approach

 

http://www.xilinx.com/support/answers/43537.html

 

 

Hope this helps

 

-Vanitha

 

 

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Professor
Professor
12,677 Views
Registered: ‎08-14-2007

Re: Comunication to DDR3 RAM using MIG


@vsrunga wrote:

@benkhoff

 

Your user interface FSM should not have any effect on calibration, write/read comamnds come into picture only after calibration.

I would suggest you to go through below XIlinx AR and follow the given debug approach

 

http://www.xilinx.com/support/answers/43537.html

 

 

Hope this helps

 

-Vanitha

 

 


I seem to recall that many of the user interface signals are required to remain zero until calib_done asserts.  On the other hand, calib_done not going high in actual hardware is likely to be another issue.  Some of those I've come across include problems with Vref, and improper termination.

-- Gabor
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