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Visitor
Visitor
7,233 Views
Registered: ‎06-14-2016

Constraint problem using Oserdes

Hi everyone,

 

I'm getting strange errors during the MAP and PAR of my design. Following the idea of XAPP1064 i'm using a BUFIO2 primitive in order to clock 2 oserdes block in master-slave mode.

 

Here is the code:

 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;

library unisim ;
use unisim.vcomponents.all ;


entity serdes_n_to_1_s8_diff  is port 	(
	clkin_p			:  in std_logic ;
	clkin_n			:  in std_logic ;	
	dataout_p		: out std_logic ;		-- output
	dataout_n		: out std_logic ;
	data_clk_p		: out std_logic ;
	data_clk_n		: out std_logic) ;	-- output
end serdes_n_to_1_s8_diff ;

architecture arch_serdes_n_to_1_s8_diff of serdes_n_to_1_s8_diff is

signal	tx_data_out 	: std_logic ;
signal	tx_clk_out 	: std_logic ;


--signal for oserdes
signal 	cascade_do	: std_logic := '0' ;			
signal 	cascade_to	: std_logic := '0' ;	
signal 	cascade_ti	: std_logic := '0' ;			
signal 	cascade_di	: std_logic := '0' ;	
signal 	cascade_do_clk	: std_logic := '0' ;			
signal 	cascade_to_clk	: std_logic := '0' ;	
signal 	cascade_ti_clk	: std_logic := '0' ;			
signal 	cascade_di_clk	: std_logic := '0' ;	
signal   reset				:  std_logic ;
signal   datain			:   std_logic_vector(7 downto 0) ;
signal 	train				:	 std_logic ; -- use in case u want the oserdes to send a fixed pattern
signal 	txserdesstrobe	: std_logic ;	
signal 	txioclk	: std_logic ;	
signal 	txioclk_clk	: std_logic ;	
signal 	freqgen_in_p	: std_logic ;	
signal 	gclk	: std_logic ;	
signal 	gclk_s	: std_logic ;	
signal 	data_clk_se :std_logic := '0';


begin


 IBUFGDS_inst : IBUFGDS
   generic map (
      DIFF_TERM => TRUE, -- Differential Termination 
      IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DEFAULT")
   port map (
      O =>freqgen_in_p,  -- Clock buffer output
      I => clkin_p,  -- Diff_p clock buffer input (connect directly to top-level port)
      IB => clkin_n -- Diff_n clock buffer input (connect directly to top-level port)
   );



Generation_oserdes_clock : BUFIO2 generic map(
      DIVIDE			=> 8,              		
      I_INVERT			=> FALSE,               	
      DIVIDE_BYPASS		=> FALSE,               	
      USE_DOUBLER		=> FALSE)               		
port map (
      I				=> freqgen_in_p,  		
      IOCLK			=> txioclk,        		
      DIVCLK			=> gclk_s,                
      SERDESSTROBE		=> txserdesstrobe) ;           
		
		
BUFG_inst : BUFG
   port map (
      O => gclk, -- 1-bit output: Clock buffer output
      I => gclk_s  -- 1-bit input: Clock buffer input
   );
		
		
--Generation_oserdes_clock2 : BUFIO2 generic map(
--      DIVIDE			=> 8,              		-- The DIVCLK divider divide-by value; default 1
--      I_INVERT			=> FALSE,               	--
--      DIVIDE_BYPASS		=> FALSE,               	--
--      USE_DOUBLER		=> TRUE)               		--
--port map (
--      I				=> freqgen_in_p,  		-- Input source clock 0 degrees
--      IOCLK			=> txioclk_clk,        		-- Output Clock for IO
--      DIVCLK			=> open,                -- Output Divided Clock
--      SERDESSTROBE		=> open) ;           	-- Output SERDES strobe (Clock Enable)


data_out : obufds port map (O => dataout_p, OB  => dataout_n, I  => tx_data_out); --output data for other DPP board

data_clk_out : obufds port map (O => data_clk_p, OB  => data_clk_n, I  => tx_clk_out); --output data clock for other DPP board

oserdes_m : OSERDES2 generic map (
	DATA_WIDTH     		=> 8, 			-- SERDES word width.  This should match the setting is BUFPLL
	DATA_RATE_OQ      	=> "SDR", 		-- <SDR>, DDR
	DATA_RATE_OT      	=> "SDR", 		-- <SDR>, DDR
	SERDES_MODE    		=> "MASTER", 		-- <NONE>, MASTER, SLAVE
	OUTPUT_MODE 		=> "SINGLE_ENDED",
	TRAIN_PATTERN		=> 0)
port map (
	OQ       		=> tx_data_out,
	OCE     		=> '1',
	CLK0    		=> txioclk,
	CLK1    		=> '0',
	IOCE    		=> txserdesstrobe,
	RST     		=> reset,
	CLKDIV  		=> gclk,
	D4  			=> datain(7),
	D3  			=> datain(6),
	D2  			=> datain(5),
	D1  			=> datain(4),
	TQ  			=> open,
	T1 			=> '0',
	T2 			=> '0',
	T3 			=> '0',
	T4 			=> '0',
	TRAIN    		=> train,
	TCE	   		=> '1',
	SHIFTIN1 		=> '1',			-- Dummy input in Master
	SHIFTIN2 		=> '1',			-- Dummy input in Master
	SHIFTIN3 		=> cascade_do,	-- Cascade output D data from slave
	SHIFTIN4 		=> cascade_to,	-- Cascade output T data from slave
	SHIFTOUT1 		=> cascade_di,	-- Cascade input D data to slave
	SHIFTOUT2 		=> cascade_ti,	-- Cascade input T data to slave
	SHIFTOUT3 		=> open,		-- Dummy output in Master
	SHIFTOUT4 		=> open) ;		-- Dummy output in Master

oserdes_s : OSERDES2 generic map(
	DATA_WIDTH     		=> 8, 			-- SERDES word width.  This should match the setting is BUFPLL
	DATA_RATE_OQ      	=> "SDR", 		-- <SDR>, DDR
	DATA_RATE_OT      	=> "SDR", 		-- <SDR>, DDR
	SERDES_MODE    		=> "SLAVE", 		-- <NONE>, MASTER, SLAVE
	OUTPUT_MODE 		=> "SINGLE_ENDED",
	TRAIN_PATTERN 		=> 15)
port map (
	OQ       		=> open,
	OCE     		=> '1',
	CLK0    		=> txioclk,
	CLK1    		=> '0',
	IOCE    		=> txserdesstrobe,
	RST     		=> reset,
	CLKDIV  		=> gclk,
	D4  			=> datain(3),
	D3  			=> datain(2),
	D2  			=> datain(1),
	D1  			=> datain(0),
	TQ  			=> open,
	T1 			=> '0',
	T2 			=> '0',
	T3  			=> '0',
	T4  			=> '0',
	TRAIN 			=> train,
	TCE	 		=> '1',
	SHIFTIN1 		=> cascade_di,	-- Cascade input D from Master
	SHIFTIN2 		=> cascade_ti,	-- Cascade input T from Master
	SHIFTIN3 		=> '1',			-- Dummy input in Slave
	SHIFTIN4 		=> '1',			-- Dummy input in Slave
	SHIFTOUT1 		=> open,		-- Dummy output in Slave
	SHIFTOUT2 		=> open,		-- Dummy output in Slave
	SHIFTOUT3 		=> cascade_do,   	-- Cascade output D data to Master
	SHIFTOUT4 		=> cascade_to) ; 	-- Cascade output T data to Master
-------------------------------

oserdes_m2 : OSERDES2 generic map (
	DATA_WIDTH     		=> 8, 			-- SERDES word width.  This should match the setting is BUFPLL
	DATA_RATE_OQ      	=> "SDR", 		-- <SDR>, DDR
	DATA_RATE_OT      	=> "SDR", 		-- <SDR>, DDR
	SERDES_MODE    		=> "MASTER", 		-- <NONE>, MASTER, SLAVE
	OUTPUT_MODE 		=> "SINGLE_ENDED",
	TRAIN_PATTERN		=> 0)
port map (
	OQ       		=> tx_clk_out,
	OCE     		=> '1',
	CLK0    		=> txioclk,
	CLK1    		=> '0',
	IOCE    		=> txserdesstrobe,
	RST     		=> reset,
	CLKDIV  		=> gclk,
	D4  			=> datain(7),
	D3  			=> datain(6),
	D2  			=> datain(5),
	D1  			=> datain(4),
	TQ  			=> open,
	T1 			=> '0',
	T2 			=> '0',
	T3 			=> '0',
	T4 			=> '0',
	TRAIN    		=> '0',
	TCE	   		=> '1',
	SHIFTIN1 		=> '1',			-- Dummy input in Master
	SHIFTIN2 		=> '1',			-- Dummy input in Master
	SHIFTIN3 		=> cascade_do_clk,	-- Cascade output D data from slave
	SHIFTIN4 		=> cascade_to_clk,	-- Cascade output T data from slave
	SHIFTOUT1 		=> cascade_di_clk,	-- Cascade input D data to slave
	SHIFTOUT2 		=> cascade_ti_clk,	-- Cascade input T data to slave
	SHIFTOUT3 		=> open,		-- Dummy output in Master
	SHIFTOUT4 		=> open) ;		-- Dummy output in Master

oserdes_s2 : OSERDES2 generic map(
	DATA_WIDTH     		=> 8, 			-- SERDES word width.  This should match the setting is BUFPLL
	DATA_RATE_OQ      	=> "SDR", 		-- <SDR>, DDR
	DATA_RATE_OT      	=> "SDR", 		-- <SDR>, DDR
	SERDES_MODE    		=> "SLAVE", 		-- <NONE>, MASTER, SLAVE
	OUTPUT_MODE 		=> "SINGLE_ENDED",
	TRAIN_PATTERN 		=> 15)
port map (
	OQ       		=> open,
	OCE     		=> '1',
	CLK0    		=> txioclk,
	CLK1    		=> '0',
	IOCE    		=> txserdesstrobe,
	RST     		=> reset,
	CLKDIV  		=> gclk,
	D4  			=> datain(3),
	D3  			=> datain(2),
	D2  			=> datain(1),
	D1  			=> datain(0),
	TQ  			=> open,
	T1 			=> '0',
	T2 			=> '0',
	T3  			=> '0',
	T4  			=> '0',
	TRAIN 			=> '0',
	TCE	 		=> '1',
	SHIFTIN1 		=> cascade_di_clk,	-- Cascade input D from Master
	SHIFTIN2 		=> cascade_ti_clk,	-- Cascade input T from Master
	SHIFTIN3 		=> '1',			-- Dummy input in Slave
	SHIFTIN4 		=> '1',			-- Dummy input in Slave
	SHIFTOUT1 		=> open,		-- Dummy output in Slave
	SHIFTOUT2 		=> open,		-- Dummy output in Slave
	SHIFTOUT3 		=> cascade_do_clk,   	-- Cascade output D data to Master
	SHIFTOUT4 		=> cascade_to_clk) ; 	-- Cascade output T data to Master
		


end arch_serdes_n_to_1_s8_diff ;

 

Here is the constraint file:

 

net "dataout_p" iostandard=lvds_25  | DIFF_TERM = TRUE;

net "dataout_n" iostandard=lvds_25  | DIFF_TERM = TRUE;

net "data_clk_p" iostandard=lvds_25 | DIFF_TERM = TRUE;

net "data_clk_n" iostandard=lvds_25 | DIFF_TERM = TRUE;

net "clkin_p"iostandard=lvds_25 | DIFF_TERM = TRUE;

net "clkin_n"iostandard=lvds_25 | DIFF_TERM = TRUE;


NET "dataout_n" LOC = N5;
NET "dataout_p" LOC = P5;
NET "clkin_n" LOC = M7;
NET "clkin_p" LOC = P7;
NET "data_clk_n" LOC = R5;
NET "data_clk_p" LOC = T5;

 

During the map i get this error:

 

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBS component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBS was chosen because the IO contains symbols and/or properties consistent
   with differential slave usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "dataout_n" (Pad Signal = dataout_n)
   	SlaveBuffer symbol "data_out/SLAVEBUF.DIFFOUT" (Output Signal = dataout_n)
   Component type involved: IOBS
   Site Location involved: N5
   Site Type involved: IOBM

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBM component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBM was chosen because the IO contains an true differential buffer symbol.
   Please double check that the types of logic elements and all of their
   relevant properties and configuration options are compatible with the
   physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "dataout_p" (Pad Signal = dataout_p)
   	BUFINV symbol "data_out/OBUFDS" (Output Signal = dataout_p)
   Component type involved: IOBM
   Site Location involved: P5
   Site Type involved: IOBS

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBS component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBS was chosen because the IO contains symbols and/or properties consistent
   with differential slave usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "data_clk_n" (Pad Signal = data_clk_n)
   	SlaveBuffer symbol "data_clk_out/SLAVEBUF.DIFFOUT" (Output Signal =
   data_clk_n)
   Component type involved: IOBS
   Site Location involved: R5
   Site Type involved: IOBM

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBM component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBM was chosen because the IO contains an true differential buffer symbol.
   Please double check that the types of logic elements and all of their
   relevant properties and configuration options are compatible with the
   physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "data_clk_p" (Pad Signal = data_clk_p)
   	BUFINV symbol "data_clk_out/OBUFDS" (Output Signal = data_clk_p)
   Component type involved: IOBM
   Site Location involved: T5
   Site Type involved: IOBS

 

I've tried to disable the LOC constraint and ISE sucessfully complete both MAP and PAR. 

 

do you have any suggestions?? if you need further information pls ask me.

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2 Replies
Highlighted
Explorer
Explorer
7,225 Views
Registered: ‎09-13-2011

Re: Constraint problem using Oserdes

I think if you remove these two lines:

NET "dataout_n" LOC = N5;
NET "data_clk_n" LOC = R5;

and change these two lines:

NET "dataout_p" LOC = P5;
NET "data_clk_p" LOC = T5;

to:

NET "dataout_p" LOC = T5;
NET "data_clk_p" LOC = P5;

 It should probably work but the layout then needs to be changed.

 

Also, I guess you want a clock out of the tx_clk_out and not data so the data drives should be 0/1 pattern:

        D4  			=> '0',
	D3  			=> '1',
	D2  			=> '0',
	D1  			=> '1',

 

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Highlighted
Visitor
Visitor
7,220 Views
Registered: ‎06-14-2016

Re: Constraint problem using Oserdes

Hi tsjorgensem, thankyou for the answer.

 -----------------------------------------------------------------

and change these two lines:

NET "dataout_p" LOC = P5;
NET "data_clk_p" LOC = T5;

to:

NET "dataout_p" LOC = T5;
NET "data_clk_p" LOC = P5;

 It should probably work but the layout then needs to be changed.

 -----------------------------------------------------------------

I've tried to change the constrains as you suggested but unfortunately  i received the same errors.   Btw the constraints i set for both the data_clock_out and the data_out were just an example. Accounting for my board layout they must be connected in any pin of the bank 2.

 -----------------------------------------------------------------

Also, I guess you want a clock out of the tx_clk_out and not data so the data drives should be 0/1 pattern:

        D4  			=> '0',
	D3  			=> '1',
	D2  			=> '0',
	D1  			=> '1',

 

Of course you are rigth, that was a copy-past error.

 -----------------------------------------------------------------

 

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