10-31-2010 07:50 AM - edited 10-31-2010 07:52 AM
I am a student,i am new to FPGA.
I am learning Verilog Language.I have done some basic experiments on Spartan 3E Kit.
I have been given a task
If possible i have to do so before Tuesday.can anyone help me with coding?
Student of M.Tech 1,
10-31-2010 11:45 AM
I would suggest that you start first with reading the datasheet for the LTC2624 to understand the interface, followed by the user guide or schematics for the board that you are using to understand how the device is configured and connected to the FPGA and then write the code to implement the interface and output the required digital SIN values.
10-31-2010 12:39 PM
Project estimate: 1 day for experienced engineer.
Project estimate for inexperienced student:
4 hours to download and install ISE
8 hours to review starter kit "standard" code to understand file structure, pinouts, etc.
3 hours to download, read, and assimilate LTC2624 datasheet
8 hours to learn SPI interface and how it works
2 hours to discover CoreGen, and DDS generator
2 days to learn basics of FSM design, and write successful basic example
2 days to learn basics of ISIM, successfully build and run a small simulation (or skip ISIM, add 2 days to debug time)
1 day to design and implement the code needed to complete the project, to the point the code compiles
1 day to test, debug, re-write, re-test the design
3 hours to document the project for submission to the professor.
student has basic understanding of what a DAC is and how it works
student knows how to locate, read, and assimilate datasheets
student understands basics of hardware design
student understands enough of Verilog language to complete the task
student understands enough of Veriilog language and ISE to interpret error/warning messages correctly
student has a proper computer, plus skills, to 'manage' and run ISE
student has access to decent facilities (scope, mostly)
Some of these tasks will take longer, some shorter. Some are concurrent with others.
this list, including the list of sub-tasks, is incomplete. there are unknown problems which will arise (e.g. disk crash)
Does your course work include project planning?
-- Bob Elkind
11-14-2010 08:29 AM
hello I am an academic user (student) , sorry for intruding with another topic, but , I can not find what I'm looking for
I am working with spartan3e . A stage of my project needs to generatE a signal with frequency = 1 to 2 MHZ.
I need to generate a signal with dds (direct digital synthesis) method . That signal is taken out of DAC LTC2624 (A,B,C,or D) and introduced in a block (PCB),
MY QUESTION IS,,, iS POSIBLE TO GENERATE A WAVEFORM WITH FREQUENCY = 1Mhz,TAKEN OUT OF THE DAC,,CONSIDERING THE 50 Mhz CLOCK ONBOARD?
11-14-2010 10:06 AM - edited 11-14-2010 10:17 AM
Some Expert will answer your query.
50 Mhz CLOCK ONBOARD? What do you mean ?
I guess 1 to 2 MHZ can be generated using DCM. Under that frequecny generate a waveform inside the FPGA and then
send it to DAC .Whats is the frequency of DAC ?
11-14-2010 11:29 AM - edited 11-14-2010 11:55 AM
A stage of my project needs to generatE a signal with frequency = 1 to 2 MHZ.
Your system will need to generate and convert data at a minimum of double the signal frequency you desire. Read up on the concept "nyquist limit".
I need to generate a signal with dds (direct digital synthesis) method.
No problem. Do you understand how DDS works?
That signal is taken out of DAC LTC2624...
Have you read the LTC2624 datasheet?
iS POSIBLE TO GENERATE A WAVEFORM WITH FREQUENCY = 1Mhz
The realistic answer is NO, and it has almost nothing to do with the 50MHz fabric clock frequency on the FPGA. The problem is the LTC2624 DAC. Look at its settling time. Look at the maximum serial bit frequency for data transfer. Look at the minimum number of serial clock cycles for transferring a single data value.
Bottom line: this DAC is too slow (conversion as well as data transfer) for 2MHz output sinewave.
Ignoring settling time (this cannot be ignored, actually), data transfer alone will barely permit 1MHz output (and only a sinewave, nothing more complex). When you add a reasonable reconstruction filter to the DAC output to filter sampling frequency noise, you are unlikely to be happy with the analogue output result.
As a student, you need to understand WHY the DAC is too slow. Then you will know enough to select a proper DAC for your application. You haven't mentioned signal distortion, amplitude, linearity, or noise requirements. You need to learn what these attributes mean, in order to design a proper sampled system.
-- Bob Elkind
11-14-2010 12:01 PM
Your reply to this thread doesn't make any sense. This might be misleading to someone who doesn't understand why your post doesn't make sense.
-- Bob Elkind