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Visitor marcus10110
Visitor
6,444 Views
Registered: ‎08-10-2009

DCM Feedback path for design with BUFIO2 & ISERDES2 (Spartan6)

Hi,

 

This question is about how to decide which components to put into the feedback path of a DCM. This is internally routed.

 

However I would also like feedback on the overall clock design in this application, as I'm very new to advanced DCM usage, and related clock domains and related clock crossing (TO/FROM constraints)

 

I am nearing the finish mark with my FPGA design, but I recently had to change the clock design to eliminate extra FIFOs and get the design to fit into the LX16.

 

My design receives it's clock from a ADC, which is outputting a 120 MHz clock, which it uses to output 8 ADC channels (DDR).

 

I need to receive this clock in the FPGA, and use it to drive 9 ISERDES2 inputs. I need to use the same clock as the source for my main system clock.

 

The overall clock topology is pretty simple:

 

120 MHz differential clock enters FPGA.

 

120 differential clock to IBUFGDS

 

IBUFGDS to two BUFIO2s (for DDR ISERDES2)

 

BUFIO2(1) uses the doubler, and set with divide = 6.

BUFIO2(2) does not use doubler, and is inverted.

 

both BUFIO2s have their IOCLK connected to my ISERDES modules, and the first BUFIO2 drives the SERDESSTROBE. This is textbook ISERDES2 using BUFIO2 in DDR mode, and all the pins are in the same half bank. So far so good.

 

BUFIO2(1) DIVCLK drives a BUFG, and this new clock drives the CLKDIV inputs on the ISERDES2 modules, which are in NETWORKING_PIPELINED mode. This clock also drives my bitslip state machine.

 

This is where things get complicated. This divided clock is 40 MHz. I need to generate a 80 MHz clock domain to run some filters in the DSP48A1 slices. I need to move that data back to the 40 MHz domain after it's filtered. 

 

This 40 MHz clock needs to be routed all over the FPGA.

 

 

My current solution:

 

Route this 40 MHz clock from the BUFG directly to the input of a DCM. Set the deskew adjust to SYSTEM_SYNCHRONOUS. Feedback set to 1x. CLKOUT_PHASE_SHIFT set to none.

 

 

I have CLK0 driving the rest of my design, with the assumption that I can cross the data from my ISERDES output directly to the clock out.

CLK0 is also routed back to the feedback input, with nothing in between.

 

I have CLK2x driving my DSP blocks, with a state machine to help move the data from 1x to 2x clock, and then another state machine to move it back (using flags and stuff, pretty basic)

 

Can I assume that the input to the DCM will be phase aligned with the output? If not, do I need to adjust the feedback path to match the input clock path?

 

Can I assume that ISE can create the TO-FROM constraints between CLK0 and CLK2X? What about a constraint between DIVCLK (the input of the DCM) to CLK0?

 

Right now, my design fits, meets timing, and simulation looks good - in behavioral, post map, and in post route - with one small hiccup in behavioral sim. (more on that later)

 

 

However, I had to hack the constraints to get the design to MAP.

 

Specifically, the MAP system said that I had a non-ideal placement of BUFIO2 and BUFG(I think), and that a dedicated route constraint needed to be used to fix it. Another thread by bassman59 suggested that there were a number of weird limitations on the BUFIO2 placements. In fact, the design would map if I used a different clock input to the DCM, but when I used the BUFG output to drive the DCM, the map failed. So I mapped it with a different clock, recorded the BUFIO2 placements, and then added these constraints:

INST "[full path removed]/U0_AdcInterface/U0_AdcSerdes/bufio2_inv_inst" LOC=BUFIO2_X2Y29;
INST "[full path removed]/U0_AdcInterface/U0_AdcSerdes/bufio2_inst" LOC=BUFIO2_X2Y28;

 

After adding this, the design mapped with the BUFG driving the DCM.

 

My questions:

1. Does the description above sound like a good way to use a single clock to drive the entire design, and the ISERDES2 modules? I am worried that usually, an input clock is routed directly to a BUFG, and then to the DCM. My clock first passes through a IOBUF2, then to a BUFG, and then the DCM.

 

2. Can I match the phase between the DCM CMK0 and the output of the BUFG which drives it?

 

3. Do I need to make changes to my feedback path to accomplish that? On a related note, is the tool inferring components in the feedback path? I assumed a clock buffer of some sort would be required, but I never created one.

 

4. Are there any negative consequences from using the constraints above to force the tools to MAP? I am worried that the tools correctly reported that the design was impossible the first time, and somehow the constraints are actually just allowing a broken design.

 

5. Are the tools creating constraints between the CLK0 & CLK2X outputs, and between the input clock and the CLK0? If so, where can I find them? I didn't see anything useful in the derived constraints report.

 

 

Also, there is an error in the behavioral sim. Specifically, the 2X clock domain picks up data from the 1x Clock domain on the same edge that the 1x domain sets up on, which is impossible. The problem doesn't show up in the post map or post route simulations though. Should I post a separate thread about this?

 

It's also worth noting that in all 3 simulations, the CLK_DIV, CLK0, and CLK2X were phase aligned.

 

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5 Replies
Scholar austin
Scholar
6,414 Views
Registered: ‎02-27-2008

Re: DCM Feedback path for design with BUFIO2 & ISERDES2 (Spartan6)

m,

 

Wow.  Lots of questions.  I will answer what I can.

 

Once the 120 MHz clock gets to the clock tree (IBUFG), from there it should go directly to what needs it.  That inckudes any DCM's (you can use as many as you like all drfiven from this one clock - once the clock is on the global clock tree from the IBUFG, it is available to every block, everywhere on the device - no need for BUFG).

 

The DCM has the CLKFB input, which drives the output phase to be aligned to CLKIN (output is shiufted until CLKIN-CLKFB=0).

 

So, is you need a CLK0 from a DCM to be aligned with some external signal, one uses feedback from the CLK0 thru/to/and back to the CLKFB input pin, either inside the device, or leaving, and returning through another IBUFG.

 

Simulation is key to reviewing the design to check the clocks.

 

And yes, timing constraints are needed.  Generally, a constraint on a clock is propagated through any/all DCM's automatically.  Review all reports.  They will tell you what is/is not going on.

 

Lastly, I would run everything from the one clock, and use slower signals as clock enables where needed.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Instructor
Instructor
6,412 Views
Registered: ‎07-21-2009

Re: DCM Feedback path for design with BUFIO2 & ISERDES2 (Spartan6)

A minor correction of Austin's comments...

 

once the clock is on the global clock tree from the IBUFG, it is available to every block, everywhere on the device - no need for BUFG).

 

IBUFG is nothing more than an IBUF located at a clock-capable IO pin.  IBUFG is not a clock distribution buffer.  So the output of the IBUFG does need a clock buffer (e.g. BUFG) for driving the clock distribution network.  In most instances, the synthesis tool will automatically insert the clock buffer into the design -- but explicit instantiation of the clock buffer is a good idea.

 

Yes, the naming of the IBUFG component is a bit misleading.

 

-- Bob Elkind

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Visitor marcus10110
Visitor
6,400 Views
Registered: ‎08-10-2009

Re: DCM Feedback path for design with BUFIO2 & ISERDES2 (Spartan6)

Thanks Austin and Bob! That helps a lot.

 

So in general, routing a clock first through a IOBUF2, dividing it by 6 there, and then routing it through BUFG and into a DCM is fine? The only external IO that is clocked by this input is connected to ISERDES2.

 

There is no need for external feedback, I just want CLK0 to be alligned with the input of the DIVCLK, so I can move data from the output of ISERDES2 directly to CLK0 without any trouble.

 

It sounds like I don't need any buffers in the feedback because I want to match the phase at the input of the DCM to the output of the DCM.

 

Here is a drawing of the complete clock layout.

input clocks.jpg

There are stars on the clocks I want phase alligned:

CLK0,

DIV_CLK (which drives both the DCM and the Bitslip state machine)

CLK2X.

 

And in the future CLKFX, which will be a integer multiple of CLK0 (not inportant now)

 

From what you've already said, it sounds like everything should be fine. However, if you see any problems with it, please let me know!

 

Thanks!

-Mark

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Historian
Historian
6,391 Views
Registered: ‎02-25-2008

Re: DCM Feedback path for design with BUFIO2 & ISERDES2 (Spartan6)


@marcus10110 wrote:

 

There is no need for external feedback, I just want CLK0 to be alligned with the input of the DIVCLK, so I can move data from the output of ISERDES2 directly to CLK0 without any trouble.

 

It sounds like I don't need any buffers in the feedback because I want to match the phase at the input of the DCM to the output of the DCM.


Correct, no need for external feedback. But to align the DCM outputs with its input, you need to connect the DCM feedback input to the buffer you'll put on the CLK0 output.

----------------------------Yes, I do this for a living.
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Instructor
Instructor
6,387 Views
Registered: ‎07-21-2009

Re: DCM Feedback path for design with BUFIO2 & ISERDES2 (Spartan6)

I would rather use a single PLL (rather than a DCM) to generate all the clocks you need, all aligned, including the 120 (or 240) MHz clock used for the ISERDES2 blocks.  Run the ISERDES2 blocks in SDR (not DDR) mode.

 

And unless you don't have enough DSP48a blocks, run two sets of DSP48a blocks in parallel (40MHz) rather than mess around with an additional 80MHz clock domain dedicated to usage by the DSP48a blocks.

 

Just my 2 cents opinion.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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